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H838532H датащи(PDF) 132 Page - Renesas Technology Corp

номер детали H838532H
подробное описание детали  16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series
PDF  508 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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H838532H датащи(HTML) 132 Page - Renesas Technology Corp

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Section 5 Power-Down Modes
Rev. 1.00 May 30, 2008 Page 112 of 484
REJ09B0436-0100
5.6
Subactive Mode
5.6.1
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ
0, or WKP7 to
WKP
0 interrupt is requested while the LSON bit in SYSCR1 is set to 1.
From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI3-1,
SCI3-2, IRQ
4 to IRQ0, or WKP7 to WKP0 interrupt is requested.
A transition to subactive mode
does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the
RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by
RES pin is the same as for standby mode; see Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are
φ
W/2, φW/4, and φW/8.



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