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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 121 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 121 Page - Renesas Technology Corp |
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121 / 508 page  Section 5 Power-Down Modes Rev. 1.00 May 30, 2008 Page 101 of 484 REJ09B0436-0100 Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Wait time = 8,192 states (initial value) 0 0 1 Wait time = 16,384 states 0 1 0 Wait time = 32,768 states 0 1 1 Wait time = 65,536 states 1 0 0 Wait time = 131,072 states 1 0 1 Wait time = 2 states (External clock mode) 1 1 0 Wait time = 8 states 1 1 1 Wait time = 16 states Note: In the case that external clock is input, set up the “Standby timer select” selection to External clock mode before Mode Transition. Also, do not set up to external clock mode, in the case that it does not use external clock. Bit 3: Low speed on flag (LSON) This bit chooses the system clock ( φ) or subclock (φ SUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON Description 0 The CPU operates on the system clock ( φ) (initial value) 1 The CPU operates on the subclock ( φ SUB) Bit 2: Reserved bit Bit 2 is reserved: it is always read as 1 and cannot be modified. |
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