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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 173 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 173 Page - Toshiba Semiconductor |
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173 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-171 7 6 5 4 3 2 1 0 Bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC Read/Write R R/W R (Cleared to zero when read) R/W After reset Undefined 0 0 0 0 0 0 0 1: Error Function Received data bit8 Parity 0: Odd 1: Even Parity addition 0: Disable 1: Enable Overrun Parity Framing 0: SCLK0 1: SCLK0 0: Baud rate generator 1: SCLK0 pin input Note 1: Serial control register for channel 1 is SC1CR (55H). Note 2: As all error flags are cleared after reading, do not test a single bit only with a bit-testing instruction. Figure 3.11.3 Serial Control Register (Channel 0, SC0CR) 0 Transmits and receives ( ) data on rising edge of SCLK0 1 Transmits and receives ( ) data on falling edge of SCLK0 Edge selection for SCLK pin (Input mode only) (Note 1) 0 Baud rate generator 1 SCLK0 pin input Select I/O interface input clock 0 Disable 1 Enable Enable parity addition 0 Odd parity 1 Even parity Addition/check of even parity Framing error flag Parity error flag Overrun error flag Cleared to zero when read. Receiving data bit8 SC0CR (0051H) |
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