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TMP93CS41 датащи(PDF) 135 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 135 Page - Toshiba Semiconductor |
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135 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-133 7 6 5 4 3 2 1 0 Bit symbol CAP2T5 EQ5T5 CAP1IN CAP12M1 CAP12M0 CLE T4CLK1 T4CLK0 Read/Write R/W W R/W R/W R/W After reset 0 0 1 0 0 0 0 0 TFF5 invert trigger 0: Disable trigger 1: Enable trigger Function Inverted when the UC value is latched to CAP2 Inverted when the up counter matches TREG5 0: Software capture 1: Don’t care Capture timing 00: Disable INT4 occurs at rising edge. 01: TI4 ↑ TI5 ↑ INT4 occurs at rising edge. 10: TI4 ↑ TI4 ↓ INT4 occurs at falling edge. 11: TFF1 ↑ TFF1 ↓ INT4 occurs at rising edge. 1: UC4 clear enable Timer 4 source clock 00: TI4 01: φT1 10: φT4 11: φT16 Figure 3.9.3 16-Bit Timer Mode Control Register (T4MOD) (1/2) 00 External clock (TI4) 01 φT1 10 φT4 11 φT16 Timer 4 input clock 0 Clear disable 1 Clear by match with TREG5 Clearing the up counter UC4 T4MOD (0038H) |
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