TMP93CS41 datasheet(126/248 Pages) TOSHIBA

126 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-124

The following explains PWM timer operations.

(1) PWM timer mode

PWM output changes under the following two conditions.

Condition 1:

•

TFF2 is cleared when the value in the up counter (UC2) matches the value set in the

TREG2.

•

TFF2 is set to 1 when a 2n

− 1 counter overflow (n = 6, 7, or 8) occurs.

Condition 2:

•

TFF2 is set to 1 when the value in the up counter (UC2) matches the value set in

TREG2.

•

TFF2 is cleared when a 2n

− 1 counter overflow (n = 6, 7, or 8) occurs.

The up counter (UC2) is cleared by a 2n

− 1 counter overflow.

The PWM timer can output 0% to 100% duty pulses because a 2n

− 1 counter overflow has

a higher priority. That is, to obtain 0% output (Always low), the mode used to set TFF2 to 0

due to overflow (PFFCR<FF2TRG1:0>

= 10) must be set and 2n − 1 (A value indicating an

overflow) must be set in TREG2. To obtain 100% output (Always high), the mode must be

changed by setting PFFCR<FF2TRG1:0>

= 11 and then TREG2 must be set to 2n − 1.

PWM timing

Figure 3.8.9 Output Waves in PWM Timer Mode

Note:

The waves pictured above are obtained in the mode in which the flip-flop is set by a

match with the timer register (TREG), and is reset by an overflow.

Overall

timing

(Note)

PWM counter

Match detect

− 1 overflow

counter clear

Timing in

detail

Match detect

− 1 overflow

Timer flip-flop

output (TO2/TO3)

− 1

+ 12n − 32n − 2

− 1

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