TMP93CS41 datasheet(120/248 Pages) TOSHIBA

120 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-118

The clock selected among fFPH, fc/16, and fs is divided by 2 and input to this prescaler.

The selection is made by the system clock control register SYSCR0<PRCK1:0>.

Resetting sets <PRCK1:0> to 00, selecting the fFPH clock input to be divided by 2. The

TRUN<PRRUN> register which controls this prescaler, is also used for the other timers. So,

this prescaler cannot be operated independently.

The 8-bit PWM timers 0 and 1 select one of the clock inputs:

φP1, φP4, and φP16, from

among the three prescaler outputs.

This prescaler also can be run or stopped by TRUN<PRRUN> as described in discussion

of the 8-bit timer.

Counting starts when <PRRUN> is set to 1. The prescaler is cleared and stops operation

when <PRRUN> is set to 0.

Resetting clears <PRRUN> and stops the prescaler.

When the IDLE1 mode (with only the oscillator operating) is used, set TRUN<PRRUN>

to “0” to reduce the power consumption of the prescaler before the “HALT” instruction is

executed.

2. Up counter

The up counter is an 8-bit binary counter which counts up using the input clock specified

by PWM0 mode register P0MOD<T2CLK1:0>.

The input clock for the up counter is selected from among the internal clocks

φP1, φP4,

and

φP16 (PWM dedicated prescaler output) depending on the value in <T2CLK1:0>.

Operating mode is set by P0MOD<PWM0M>. At reset, <PWM0M> is initialized to “0”,

and thus the up counter is placed in PWM mode. In PWM mode, the up counter is cleared

when a 2n

− 1 overflow occurs; in timer mode, the up counter is cleared at compare and

match.

Count/stop and clear of the up counter can be controlled for each PWM timer using the

timer operation control register TRUN. Resetting clears all up counters and stops all PWM

timers.

3. Timer register

The 8-bit register is used for setting a time interval. When the value set in the timer

comparator becomes active.

Timer register TREG2 is paired with a register buffer to make a double buffer structure.

TREG2 controls double buffer enable/disable by P0MOD<DB2EN>. The double buffer is

disabled when <DB2EN>

= 0, and enabled when <DB2EN> = 1.

In double buffer enable state, data are transferred from register buffer to timer register

when a 2n

− 1 overflow occurs in PWM mode, or when compare and match occur in 8-bit

timer mode. A PWM timer can be operated in timer mode in double buffer enable state,

whereas timers 0 and 1 cannot.

At reset, <DB2EN> is initialized to 0 to disable the double buffer. The same value is set in

both the register buffer and the timer register. To use the double buffer, write the data in

the timer register first, then set <DB2EN> to 1 and write the following data in the register

buffer.

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