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TMPR4937 датащи(PDF) 111 Page - Toshiba Semiconductor

номер детали TMPR4937
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 датащи(HTML) 111 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-11
7.3.6.3
Ready Mode
When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by
Ready input from an external device. Ready input is internally synchronized. See Section “7.3.7.5
Ready Input Timing” for more information regarding the operation timing.
When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is
performed to see whether the Ready signal was asserted. Since EBCCRn.WT[0] is used to indicate
the ACK*/ Ready Static/Dynamic mode, it is not used for setting the Wait cycle count. Therefore,
the Wait cycle count that can be set by the Ready mode is 0, 2, 4, 6, …, 62.
When the number of wait cycles is 0, Ready check is started in 1 cycle after asserting the CE*
signal. When the number of wait cycle is other than zero, after waiting only for the specified
number of cycles, Ready check is started.
The Ready mode does not support Burst access by the internal bus.
Figure 7.3.3 Ready Mode
SYSCLK
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Input)
EBCCRn.PWT:WT=2
CE*
Start Ready Check
EBCCRn.SHWT=0



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