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TMPR4937 датащи(PDF) 85 Page - Toshiba Semiconductor

номер детали TMPR4937
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 датащи(HTML) 85 Page - Toshiba Semiconductor

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Chapter 5 Configuration Registers
5-5
Bit
Mnemonic
Field Name
Description
Initial Value Read/Write
12:10 PCIDIVMODE PCICLK
Frequency
Division Ratio
Specifies the frequency division ratio of the PCI bus clock
output (PCICLK[5:0]) frequency to the clock frequency
(CPUCLK) of the TX49/H3 core.
001: PCICLK frequency
= CPUCLK frequency ÷ 4
011: PCICLK frequency
= CPUCLK frequency ÷ 4.5
101: PCICLK frequency
= CPUCLK frequency ÷ 5
111: PCICLK frequency
= CPUCLK frequency ÷ 5.5
000: PCICLK frequency
= CPUCLK frequency ÷ 8
010: PCICLK frequency
= CPUCLK frequency ÷ 9
100: PCICLK frequency
= CPUCLK frequency ÷ 10
110: PCICLK frequency
= CPUCLK frequency ÷ 11
ADDR[11:10]
,0
R/W
9:8
⎯
Reserved
⎯
⎯
⎯
7:6
SYSSP
SYSCLK
frequency
division ratio
Indicates the frequency division ratio of the SYSCLK
frequency to the G-Bus clock frequency (GBUSCLK).
LL: 00: SYSCLK frequency
= GBUSCLK frequency ÷ 4
LH: 01: SYSCLK frequency
= GBUSCLK frequency ÷ 3
HL: 10: SYSCLK frequency
= GBUSCLK frequency ÷ 2
HH: 11: SYSCLK frequency
= GBUSCLK frequency
ADDR[14:13] R
5:3
⎯
Reserved
⎯
⎯
⎯
2
ENDIAN
Endian
Indicates the TX4937 endian mode setting.
L: 0 = Little endian mode
H: 1 = Big endian mode
ADDR[12]
R
1
ARMODE
ACK*/READY
Mode
Selects an ACK*/READY signal operation mode for the
external bus controller (refer to Section 7.3.6).
0 = ACK*/READY dynamic mode
1 = ACK*/READY static mode
0
R/W
0
ACEHOLD
ACE Hold
Specifies the hold time of an address relative to the external
bus controller ACE* signal (refer to Section 7.3.4).
0 = Switch the address at the same time when the ACE*
signal is deasserted.
1 = Switch the address one clock cycle after the ACE* signal
is deasserted.
1
R/W
Figure 5.2.1 Chip Configuration Register (3/3)



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