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TMPR4937 датащи(PDF) 113 Page - Toshiba Semiconductor

номер детали TMPR4937
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 датащи(HTML) 113 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-13
7.3.7
Access Timing
7.3.7.1
SHWT Option
The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel
Control Register is a value other than “0.” This option inserts Setup cycles and Hold cycles
between signals as follows.
Setup cycle: CE* from ADDR, OE* from CE*, BWE* from CE*, SWE* from CE*.
Hold cycle: ADDR from CE*, CE* from OE*, CE* from BWE*, CE* from SWE*
This option is used for I/O devices that are generally slow. All Setup cycles and Hold cycles
will be identical, so each cycle cannot be set individually.
The SHWT mode cannot be used by the Page mode. The SHWT mode can be used by all other
modes, but there is one restriction: the internal bus cannot use Burst access.
The hold cycles of DATA relative to SWE* and BWE* are fixed at one clock cycle, regardless
of the settings of the SHWT option. When the SHWT option is disabled, the setup cycles of SEW*
and BWE* relative to CE*, and the hold cycles of OE*, SEW* and BWE* relative to CE* are one
clock cycle.
Figure 7.3.5 SWHT Disable (Normal Mode, Single Read/Write Cycle)
SYSCLK
CE*/BE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Output)
EBCCRn.PWT:WT=0
EBCCRn.SHWT=0
SWE*/BWE*



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