TMPR4937 datasheet(108/552 Pages) TOSHIBA

номер детали	TMPR4937

подробное описание детали	64-Bit TX System RISC TX49 Family

PDF	552 Pages

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производитель	TOSHIBA [Toshiba Semiconductor]

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Chapter 7 External Bus Controller

7-8

7.3.5.3

8-bit Bus Width Mode

DATA[7:0] becomes valid.

Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20],

which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the

address is shifted up two bits or more relative to the 32-bit bus mode when output. As a result, the

maximum memory size of the 8-bit bus mode is 256 MB.

Table 7.3.6 Address Output Bit Correspondence in the 8-bit Mode

ADDR Bit

19 18 17 16 15 14 13 12 11 10 9

Upper Address

27 26 25 24 23 22 21 20

Lower Address

19 18 17 16 15 14 13 12 11 10

When a Single cycle that accesses 1-Byte data is executed, 8-bit access is executed only once on

the external bus. 8-bit access is executed twice when performing 1-half-word access. 8-bit access

is executed four times when performing 1-word access. 8-bit access is executed eight times when

performing 1-double-word access. When a Burst cycle is executed, eight 8-bit cycles are executed

for each Burst access when the Bus cycle tries to request a byte combination other than double-

word data.

TMPR4937 датащи(PDF) 108 Page - Toshiba Semiconductor