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TMPR4937 датащи(PDF) 89 Page - Toshiba Semiconductor

номер детали TMPR4937
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 датащи(HTML) 89 Page - Toshiba Semiconductor

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Chapter 5 Configuration Registers
5-9
Bit
Mnemonic
Field Name
Description
Initial Value Read/Write
8
SEL1
Shared-Pin
Status 1
Indicates which function, PIO[15:8] or CB[7:0], the shared pins
are set to.
L: 0 = The shared pins are set to PIO[15:8].
H: 1 = The shared pins are set to CB[7:0].
ADDR[18]
R
7:4
⎯
Reserved
⎯
⎯
⎯
3
DMASEL3
DMA Request
Select 3
Selects a DMA request used by DMA controller 0 channel 3.
0: DMAREQ[3] (external)
1: SIO channel 0 transmission (internal)
0
R/W
2
DMASEL2
DMA Request
Select 2
Selects a DMA request used by DMA controller 0 channel 2.
0: DMAREQ[2] (external)
1: SIO channel 0 reception (internal)
0
R/W
1
DMASEL1
DMA Request
Select 1
Selects a DMA request used by DMA controller 0 channel 1.
00: DMAREQ[1] (external)
01: SIO channel 1 transmission (internal)
0
R/W
1:0
DMASEL0
DMA Request
Select 0
Selects a DMA request used by DMA controller 0 channel 0.
00: DMAREQ[0] (external)
01: SIO channel 1 reception (internal)
0
R/W
Figure 5.2.3 Pin Configuration Register (3/3)



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