TMPR4937 datasheet(69/552 Pages) TOSHIBA

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Chapter 4 Address Mapping

4-1

Address Mapping

This chapter explains the physical address map of TX4937.

Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details

of mapping to a physical address from the virtual address of TX49/H3 core.

4.1

TX4937 Physical Address Map

TX4937 supports up to 64G (236) bytes of physical address.

Following resources are to be allocated in the physical address of the TX4937.

•

TX4937 Internal registers (refer to “4.2 Register Map”)

•

SDRAM (refer to “9.3.2 Address Mapping”)

•

External Devices such as ROM, I/O Devices (refer to “7.3.3 Address Mapping”)

•

PCI Bus (refer to “10.3.4 Initiator Access”)

Each resource is to be allocated in any physical addresses by the register setup. Refer to the explanation of

each controller for the details of the mapping.

At initialization, only the internal registers and the memory space which stores the TX49/H3 core reset

vectors are allocated shown as Figure 4.1.1. Usually ROM connected to the external bus controller channel 0

is used for the memory device that stores the reset vectors. TX4937 also supports using the memories on PCI

bus as the memory device stores the reset vectors. Refer to “10.3.12 PCI Boot Configuration” for detail

about this.

Figure 4.1.1 Physical Address Map at Initializing System

It is possible to access a resource of TX4937 as a PCI target device through PCI bus. About how to

allocate resources of TX4937 to the PCI bus address space, refer to §10.3.5 Target Access.

TX4937 Internal Register

External Bus Controller Channel 0

64 K Bytes

0xF_FFFF_FFFF

0xF_FF1F_FFFF

0xF_FF1F_0000

0x0_1FFF_FFFF

0x0_1FC0_0000

0x0_0000_0000

4 M Bytes

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