TMPR4937 datasheet(61/552 Pages) TOSHIBA

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Chapter 3 Signals

3-7

3.1.9

AC-link Interface Signals

Table 3.1.9 AC-link Interface Signals

Signal Name

Type

Description

Initial State

ACRESET*

Output

AC '97 Master H/W Reset

ACRESET* shares the pin with the DMAREQ[2] signal. The boot configuration signal on

the ADDR[9] pin selects between ACRESET* and DMAREQ[2] (refer to Section “3.3 Pin

multiplex”).

Selected by

ADDR[9]

L: Low

H: Input

SYNC

Output

48 kHz Fixed Rate Sample Sync

SYNC shares the pin with the DMAACK[2] signal. The boot configuration signal on the

ADDR[9] pin selects between SYNC and DMAACK[2] (refer to Section “3.3 Pin

multiplex”).

Selected by

ADDR[9]

L: Low

H: High

SDOUT

Output

Serial, Time Division Multiplexed, AC '97 Output Stream

SDOUT shares the pin with the PIO[4] signal. The boot configuration signal on the

ADDR[9] pin selects between SDOUT and PIO[4] (refer to Section “3.3 Pin multiplex”).

Selected by

ADDR[9]

L: Low

H: Input

SDIN[1]

Input

Serial, Time Division Multiplexed, AC ‘97 Input Stream

When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the

value of register, please ask the Engineering Department in Toshiba).

Input

SDIN[0]

Input

Serial, Time Division Multiplexed, AC '97 Input Stream

SDIN[0] shares the pin with the PIO[3] signal. The boot configuration signal on the

ADDR[9] pin selects between SDIN[0] and PIO[3] (refer to Section “3.3 Pin multiplex”).

When this pin is used as SDIN[0], pull down by the resister on the board. (Regarding the

value of register, please ask the Engineering Department in Toshiba).

Input

BITCLK

Input

12.288 MHz Serial Data Clock

BITCLK shares the pin with the PIO[2] signal. The boot configuration signal on the

ADDR[9] pin selects between BITCLK and PIO[2] (refer to Section “3.3 Pin multiplex”).

When this pin is used as BITCLK, pull down by the resister on the board. (Regarding the

value of register, please ask the Engineering Department in Toshiba).

Input

3.1.10 Interrupt Signals

Table 3.1.10 Interrupt Signals

Signal Name

Type

Description

Initial State

NMI*

Input

Non-Maskable Interrupt

Non-maskable interrupt signal.

Input

INT[5:0]

Input

External Interrupt Requests

External interrupt request signals.

INT[4:3] share pins with other function signals (refer to Section “3.3 Pin multiplex”).

Input

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