TMPR4937 datasheet(48/552 Pages) TOSHIBA

48 / 552 page

Chapter 1 Overview and Features

1-2

1.2.1

Features of the TX49/H3 core

The TX49/H3 core is a high-performance, low power consumption 64-bit RISC CPU core that

Toshiba developed.

•

64-bit operation

•

32 64-bit integer general-purpose registers

•

64 GB physical address space

•

Optimized 5-stage pipeline

•

Instruction Set

Upwards compatible MIPS III ISA

Added 3-operand multiply instruction, MAC (multiply accumulate) instruction, and PREF (pre-

fetch) instruction

•

Supports 32 KB Instruction cache, 32 KB Data cache, 4-way set associative, and the lock function

•

MMU (Memory Management Unit)

48 double entry (odd/even) joint TLB

•

On-chip IEEE754-compatible single-precision and double-precision FPU

•

4-stage write buffer mounted

•

Debugging Support Unit: EJTAG

1.2.2

Features of TX4937 peripheral functions

(1) External Bus Controller (EBUSC)

The External Bus Controller generates the signals necessary to control external memory and

external I/O devices.

•

Has 8-channel Chip Select signal, can control up to 8 external devices

•

Supports access of ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, Flash

ROM, and I/O devices

•

Can set data bus width to 32 bits, 16 bits, or 8 bits for each channel

•

System clock for External Bus Controller (SYSCLK) frequency is up to 133 MHz (For

relationship between CPU clock and this system clock, see Section 6.1)

•

Can select full speed, 1/2 speed, 1/3 speed , or 1/4 speed for each channel

•

Can set timing for each channel

Can set up and set the Hold interval of the Address, Chip Enable, Write Enable, and Output

Enable signals

•

Supports access of devices with a 32-bit wide data bus in memory sizes from 1 MB to 1 GB.

Supports access of devices with a 16-bit wide data bus in memory sizes from 1 MB to 512

MB. Supports access of devices with an 8-bit wide data bus in memory sizes from 1 MB to

256 MB.

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