TMPR4937 datasheet(70/552 Pages) TOSHIBA

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Chapter 4 Address Mapping

4-2

4.2

4.2.1

Addressing

TX4937 internal registers are to be accessed through 64 K bytes address space that is based on

physical address 0xF_FF1F_0000 or pointed address by RAMP register (refer to 5.2.7). Figure 4.2.1

shows how to generate internal register address. Physical address 1 and physical address 2 shown

Figure 4.2.1 access the same register.

In TX49/H3 Core, the physical address form 0xF_FF00_0000 to 0xF_FF3F_FFFF are uncached

mapped to the virtual address form 0xFF00_0000 to 0xFF3F_FFFF (32 bit mode) /form

0xFFFF_FFFF_FF00_0000 to 0xFFFF_FFFF_FF3F_FFFF (64 bit mode).

This space includes the region form 0xF_FF1F_0000 allocated TX4937 internal registers at

initialization.

Figure 4.2.1 Generating Physical Address for a Internal Register

4.2.2

Ways to Access to Internal Registers

3 ways to access to the internal registers of TX4937 are supported. First is 32-bit register access.

Second is 64-bit register access. Last is PCI configuration register access in PCI satellite mode.

32-bit register supports 32-bit size access only. Another size access without 32-bit size is undefined.

64-bit register supports both 64-bit size access and two times 32-bit size access. In each Endian

mode, 32-bit size access is performed shown as Table 4.2.1.

When the build-in PCI controller works in the satellite mode (refer to “10.3.1 Terminology

Explanation”), PCI configuration registers are to be accessed through PCI bus in configuration cycles. It

is possible to access to the arbitrary size of PCI configuration register as always Little Endian space

regardless the system setup.

Table 4.2.1 32-bit Size Access to 64-bit Register

Address

Big Endian

(Bit which are accessed)

Little Endian

(Bit which are accessed)

0x*_****_***0

0x*_****_***8

[63........32] [31........0]

########

[63........32] [31........0]

########

0x*_****_***4

0x*_****_***C

[63........32] [31........0]

########

[63........32] [31........0]

########

(######## means 32 bits data (upper 32 bits or lower 32 bits) which are accessed.)

Base Address

(0xF_FF1F_0000)

Offset Address

Physical Address 1

Base Address Register

(RAMP)

Offset Address

Physical Address 2

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