TMPR4937 datasheet(96/552 Pages) TOSHIBA

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Chapter 6 Clocks

6-2

Table 6.1.1 TX4937 Clock Signals (1/2)

Clock

Input/Output

Description

Configuration Signals

(Refer to Section

3.2.)

Related Registers

(Refer to Chapters 5

and 10.)

MASTERCLK Input

Master input clock for the TX4937.

The TX4937 internal clock generator multiplies or

divides MASTERCLK to generate internal clock

pulses.

⎯

CPUCLK

Internal signal Clock supplied to the TX49/H3 core.

PLL1 in the TX4937 generates CPUCLK by

multiplying MASTERCLK. Boot configuration

signals ADDR[3:0] can set the frequency ratio of

CPUCLK to MASTERCLK.

ADDR[3:0]

HHHH = 2 times MASTERCLK

HHHL = 2.5 times MASTERCLK

HHLH = 3 times MASTERCLK

HHLL = 4 times MASTERCLK

LHHH = 4.5 times MASTERCLK

HLHH = 8 times MASTERCLK

HLHL = 10 times MASTERCLK

HLLH = 12 times MASTERCLK

HLLL = 16 times MASTERCLK

LLHH = 18 times MASTERCLK

ADDR[3:0]

CCFG.DIVMODE[3:0]

GBUSCLK

Internal signal Clock supplied to peripheral blocks on the G-Bus.

PLL1 in the TX4937 generates GBUSCLK by

multiplying MASTERCLK. Boot configuration

signal ADDR[2] can set the multiplier value.

ADDR[2]

L = 4 times MASTERCLK

H = 1 times MASTERCLK

ADDR[2]

CCFG.DIVMODE[2]

IMBUSCLK

Internal signal Clock supplied to peripheral modules on the IM-

Bus.

The frequency of IMBUSCLK is half that of

GBUSCLK.

⎯

SYSCLK

Output

System clock output from the TX4937. Used by

the devices connected to the external bus

controller (EBUSC).

Boot configuration signals ADDR[14:13] can set

the frequency ratio of SYSCLK to GBUSCLK.

ADDR[14:13]

LL: GBUSCLK divided by 4

LH: GBUSCLK divided by 3

HL: GBUSCLK divided by 2

HH: GBUSCLK divided by 1

The SYSCLKEN bit of the PCFG register can

disable the output of SYSCLK.

Note: To use SYSCLK to access external

devices, the SYSCLK rate must match the

EBUSC channel operating rate. For details,

refer to Section 7.3.8.

ADDR[14:13]

CCFG.SYSSP

PCFG.SYSCLKEN

SDCLK[3:0]

Output

Clock supplied to SDRAM. The frequency of

SDCLK[3:0] is the same as that of GBUSCLK.

The SDCLKEN[3:0] field of the PCFG register can

disable the output of SDCLK[3:0] on a per bit

basis.

⎯

PCFG.DRVCK[3:0]

PCFG.SDCLKEN[3:0]

SDCLKIN

Input/output

Reference clock used to latch input data signals

from SDRAM.

The clock output from SDCLK should be

connected to SDCLKIN via a feedback line

outside the TX4937.

⎯

PCFG.DRVCKIN

(PCFG.SDCLKDLY)

(PCFG.SDCLKINEN)

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