PIC16F684 datasheet(121/192 Pages) MICROCHIP

121 / 192 page

DS41202F-page 119

PIC16F684

DECFSZ

Decrement f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(f) - 1

→ (destination);

skip if result = 0

Status Affected:

None

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOP is

executed instead, making it a

2-cycle instruction.

GOTO

Unconditional Branch

Syntax:

[ label ]

GOTO k

Operands:

≤ k ≤ 2047

Operation:

→ PC<10:0>

PCLATH<4:3>

→ PC<12:11>

Status Affected:

None

Description:

GOTO

is an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a

two-cycle instruction.

INCF

Increment f

Syntax:

[ label ]

INCF f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(f) + 1

→ (destination)

Status Affected:

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ]

INCFSZ f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(f) + 1

→ (destination),

skip if result = 0

Status Affected:

None

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOP is executed

instead, making it a 2-cycle

instruction.

IORLW

Inclusive OR literal with W

Syntax:

[ label ]

IORLW k

Operands:

≤ k ≤ 255

Operation:

(W) .OR. k

→ (W)

Status Affected:

Description:

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

IORWF

Inclusive OR W with f

Syntax:

[ label ]

IORWF

f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(W) .OR. (f)

→ (destination)

Status Affected:

Description:

Inclusive OR the W register with

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

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