PIC16F684 datasheet(50/192 Pages) MICROCHIP

50 / 192 page

PIC16F684

DS41202F-page 48

6.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

6.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKOUT),

Timer1 can use the LP oscillator as a clock source.

6.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

6.4

Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in

between pins OSC1 (input) and OSC2 (amplifier

output). The oscillator is enabled by setting the

T1OSCEN control bit of the T1CON register. The

oscillator will continue to run during Sleep.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when the oscillator is in the LP mode. The

user must provide a software time delay to ensure

proper oscillator start-up.

TRISA5 and TRISA4 bits are set when the Timer1

oscillator is enabled. RA5 and RA4 bits read as ‘0’ and

TRISA5 and TRISA4 bits read as ‘1’.

6.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow or carry out of TMR1L to TMR1H

between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR reset

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON 0) when

T1CKI is high then Timer1 is enabled

(TMR1ON=1) when T1CKI is low.

See Figure 6-2

Note:

The oscillator requires a start-up and

stabilization

time

before

use.

Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

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