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PIC16F684 датащи(PDF) 58 Page - Microchip Technology |
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PIC16F684 датащи(HTML) 58 Page - Microchip Technology |
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58 / 192 page ![]() PIC16F684 DS41202F-page 56 © 2007 Microchip Technology Inc. FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM FIGURE 8-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM DQ EN To C1OUT pin RD CMCON0 Set C1IF bit Q3*RD CMCON0 Reset To Data Bus C1INV DQ EN CL Q1 Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC). 2: Q1 is held high during Sleep mode. C1 C2SYNC DQ EN To C2OUT pin RD CMCON0 Set C2IF bit Q3*RD CMCON0 Reset To Data Bus C2INV Timer1 clock source(1) 0 1 To Timer1 Gate DQ DQ EN CL Q1 Note 1: Comparator output is latched on falling edge of Timer1 clock source. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. C2 |
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