PIC16F684 datasheet(62/192 Pages) MICROCHIP

62 / 192 page

PIC16F684

DS41202F-page 60

A persistent mismatch condition will preclude clearing

the CxIF interrupt flag. Reading CMCON0 will end the

mismatch condition and allow the CxIF bit to be

cleared.

FIGURE 8-6:

COMPARATOR

INTERRUPT TIMING W/O

CMCON0 READ

FIGURE 8-7:

COMPARATOR

INTERRUPT TIMING WITH

CMCON0 READ

8.6

Operation During Sleep

The comparator, if enabled before entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in

Section 15.0

“Electrical

Specifications”.

the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comparator. The comparator is turned off

by selecting mode CM<2:0> = 000 or CM<2:0> = 111

of the CMCON0 register.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the device from Sleep, the CxIE bit of the PIE1 register

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the interrupt service routine.

8.7

Effects of a Reset

A device Reset forces the CMCON0 and CMCON1

registers to their Reset states. This forces the Compar-

ator module to be in the Comparator Reset mode

(CM<2:0> = 000). Thus, all comparator inputs are

analog inputs with the comparator disabled to consume

the smallest current possible.

Note 1: If a change in the CM1CON0 register

(CxOUT) should occur when a read oper-

ation is being executed (start of the Q2

cycle), then the CxIF Interrupt Flag bit of

the PIR1 register may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is stable.

Allow about 1

μs for bias settling then clear

the mismatch condition and interrupt flags

before enabling comparator interrupts.

CxIN+

CxOUT

Set CMIF (level)

CMIF

TRT

reset by software

CxIN+

CxOUT

Set CMIF (level)

CMIF

TRT

reset by software

cleared by CMCON0 read

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