ADBMS2950BCCSZ datasheet(69/97 Pages) AD

69 / 97 page

Data Sheet

ADBMS2950B

Rev. 0 | Page 69 of 97

current further increases with IO current sourced by the pins

GPO, OCA, OCB, and VREF1P25.

If the VREG pin is required to support any additional load, a

transistor with a higher beta value may be required. The power

dissipation of the NPN and the collector series resistor must be

considered when selecting appropriate components. The NPN's

collector can be powered from any voltage source that is a

minimum of 6V above GND. In Figure 48, the voltage source

that supplies VDD is used.

A 47 Ω, 100 nF RC-decoupling network is recommended for

the collector power connection for filtering and protecting the

NPN from transients. Filter the DRIVE pin by adding a 10 Ω,

10 nF RC to the base of the NPN. The emitter output is

recommended to be filtered with a ferrite bead for best EMC

and EMI performance. Alternatively, a 0 Ω resistor can be

placed to allow the option to change to a ferrite. The VREG pin

must be bypassed with a 1 μF reservoir capacitor. Avoid larger

capacitance because this increases the wake-up time of the

ADBMS2950B. Choose a transistor with adequate thermal

dissipation.

Figure 48. VREG Power Source Using NPN Pass Transistor

11V to 20V Supply and 5V Step-Down Regulator

The NPN transistor linear regulator can be replaced by a buck

regulator to improve efficiency and reduce power dissipation as

shown in the upper right section of Figure 47. The DRIVE pin

can be left unconnected in this scenario.

5V Supply and 11V to 20V Step-Up Regulator

The VREG pin can be supplied directly by an external 5V, supply

for example, an isolated 5VIN to 5VOUT ADuM derivative from

the Analog Devices isoPower series. The 11V to 20V supply for

VDD can be generated through an additional step-Up converter

as shown in Figure 47 lower left. A low-power boost regulator

or charge pump can be used. The DRIVE pin can be left

unconnected in those scenarios.

5V Supply and 14V Charge Pump

Because of the very low VDD power requirements in the order of

sub-milliampere over the full-operating temperature range (see

Table 12) plus optional GPO sourcing current for external

circuits, a simple charge-pump circuitry using an inverting

Schmitt-Trigger supplied by 5V (VREG) can be used for this

purpose. The supply current of the Schmitt-Trigger vs. the

analog input signal generated by the RC circuitry must be

considered. A suitable device, which does not respond with

excessive supply current while the input signal is around the

tripping points, is the 74HC2G14GW-Q100H from Nexperia.

Figure 49 shows the recommended implementation with an

oscillator frequency set to ~190 kHz.

Figure 49. Inverting Schmitt-Trigger Charge Pump Voltage Trippler from VREG

= 5V to VDD ~14V

Intermediate VDD Voltages

The VDD pin must be operated in either VDD = VREG or in 11V ≤

VDD ≤ 20V mode to achieve the specified performance.

However, depending on the selected power supply topology

and/or the presence of faults in the system, the VDD pin may see

a voltage that is above VREG but below 11V for some time. As the

VDD voltage drops below a level of about 8V, the VDRUV bit is

asserted, and the DRIVE pin no longer provides its 5.7V output.

This reduces the supply current drawn by the VDD pin. In cases

where VREG is supplied through an external NPN, this also shuts

down the IC. In cases where VREG is powered externally and

does not leave its specified supply range, the IC operation

including communication and measurement accuracy are not

affected. The GPO high-level output voltage follows the VDD pin

voltage throughout.

PROTECTION FEATURES

The ADBMS2950B incorporates various ESD safeguards to

ensure robust performance. An equivalent circuit showing the

specific protection structures is shown in Figure 50. Zener-like

protection structures are shown with their nominal clamp

voltage, and the unmarked diodes exhibit standard PN junction

behavior with an expected forward voltage between 0.4V and

0.8V.

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