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ADBMS2950BCCSZ датащи(PDF) 59 Page - Analog Devices |
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ADBMS2950BCCSZ датащи(HTML) 59 Page - Analog Devices |
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59 / 97 page ![]() Data Sheet ADBMS2950B Rev. 0 | Page 59 of 97 • When set to open-drain mode through GPOxOD = 1 and to high-impedance state through GPOxC = 1, the GPOs become inputs effectively. • GPO6 can be configured to output 200 kHz, 50% duty-cycle square wave signal (GPO6C). The ADBMS2950B features four GPIO pins to fulfill the following functions: • General-purpose static input/output signals. • Connectivity to local SPI or I2C peripheral (see COMM Interface). • Fault Output. The GPIOs provide the following features: • Open-drain output control up to VREG voltage (GPIO1C to GPIO4C). • Single-threshold readback (GPIO1L to GPIO4L). • GPIO1 can output the fault status of the device (GPIO1FE). • GPIO2 can signal the end-of-conversion of the OC1ADC (GPIO2EOC). An external SPI or I2C peripheral can be connected to the GPIO/GPO pins. Often, this is an EEPROM to store calibration data, for example, the shunt resistance value of the ratios of external resistive dividers. Access to external serial peripheral devices is provided through the COMM commands controlled by the host. The following serial controller interface connections are supported: • I2C peripheral devices. • 3-wire SPI peripheral devices. • 4-wire SPI peripheral devices. Additional chip-select lines for SPI communication can be provided through the GPOs. GPO Operation The six GPOs are controlled through the configuration A register CFGA. It provides the open-drain mode enable bits (GPO1OD to GPO6OD) and output state control bits (GPO1C to GPO6C) for each individual GPOx pin. Additionally, for the GPO6, a clock output mode can be activated through its 2-bit GPO6C configuration bit field. After reset, all GPOs default to the high-impedance mode. Figure 41. GPO Model Notes: 1. The GPO6L and GPO6H bits are not defined, where GPO6 has been configured in clock output mode. 2. The GPOxL and GPOxH read-only bits are redundantly read by SPI1 and SPI2 and can trigger a false SPIFLT event if GPO is exposed to dynamic signals or to extreme time constants. 3. When a GPOx pin is configured in open-drain mode and externally pulled up to a voltage lower than VDD, the GPOxH readback bit should not be used. Table 79. Relation of GPOxOD, GPOxC Configuration to GPOx Mode and State GPOxOD GPOxC GPOx Mode GPOx State 0 0 Push-Pull Pull low to GND. 0 1 Push-Pull Push high to VDD. 1 0 Open-Drain Pull low to GND. 1 1 Open-Drain High impedance. The status of the six GPOs is available in the STAT register and can be readback with the RDSTAT command. There are two read-only bits for each GPO, reporting two different threshold levels: |
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