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Data Sheet

ADBMS2950B

Rev. 0 | Page 61 of 97

The four open-drain output mode GPIOs are controlled

through the CFGB register. They can be pulled up to the VREG

voltage by external pull-up resistors. After reset, all GPIOs

default to a high-impedance state.

One of the GPIOs, GPIO1, can be configured as a fault output

by the GPIO1FE bit. The fault events that contribute to the

FAULT pin are the same as signaled through the overcurrent

output pins. Where enabled as a fault output, the pin drives low

when no fault is pending and goes to a high-impedance state if

a fault is pending. A pull-up resistor is expected externally. By

default, this function is not enabled, and GPIO1 behaves as the

other GPIO pins. The GPIO1FE fault behavior is active high

such that the occurrence of a reset is also signaled as a faulty

state.

The GPIO2 also provides an alternative functionality. It is

enabled by the GPIO2EOC bit. If set, the GPIO2 no longer

outputs the state of the GPIO2C bit, but instead provides an

output pulse every time the OC1ADC completes a conversion.

All four GPIOs can also be purposed for the COMM

functionality. Even in COMM mode, the GPIOs are open-drain

outputs. Therefore, an external pull-up resistor is required on

these ports. The COMM function is enabled by the dedicated

COMM commands. However, for the correct COMM

functionality, the GPIOxC bits of the involved GPIOs must be

set to 1 in the CFGB register to ensure that the pins are not

overruled to a low state. At any time, the GPIOxC bits can be

used to overrule the COMM function and to force a GPIO low.

The actual state of the GPIOs is available in the STAT register.

The GPIOs and GPOs can be read by the same RDSTAT

command to get coherent data. The readback is also functional

when the GPIOs are operated in COMM mode, or when the

GPIO1FE and GPIO2EOC bit are set. However, the signals may

be dynamic and are not further synchronized nor gated.

The GPIO readback features only one threshold level. If the bits

in the STAT register read zero, the GPIO is confirmed to be low.

There is no function to confirm the voltage level, when the

ADBMS2950B does not pull the signal low. Where needed, the

signal can be externally looped back to any of the V1-V10

inputs.

I2C/SPI Controller

The input/output ports GPIO1 to GPIO4 can be used as an I2C

or a SPI controller port to communicate with an I2C or SPI

peripheral.

The SPI3W bit in the CFGA register specifies whether a 3-wire

or 4-wire SPI protocol is used. The SPI mode of the SPI

controller on the ADBMS2950B is not configurable but fixed to

Mode 3 (CPHA = 1 and CPOL = 1), which makes it compatible

to the peripheral designed for this mode and for Mode 0

(CPHA = 0 and CPOL = 0). Both modes sample the data on the

rising clock edge and differ only in the Idle clock state.

Table 80 shows the assignment of the GPIOs to the serial

controller pins. GPIOs not used by the serial controller are free

to be used for other purposes. For the SPI controller, up to six

additional CS lines can be implemented using the GPO1 to

GPO6 pins (GPOx shown in Table 80) by keeping the default

CS of the SPI controller de-asserted (high) while activating one

of the GPOx through a write to CFGA.

Table 80. Serial Controller Pin Assignment

SPI (SPI3W = 0)

SPI (SPI3W = 1)

I2C

GPIO1

SDIM

GPIO2

CSBM

GPIO3

SDOM

SDIOM

SDA

GPIO4

SCKM

SCL

GPOx

CSBMx

Table 81. Serial Controller Signal Description

Signal

Description

CSBM, CSBMx

SPI Controller Chip Select Output.

SDIM

SPI Controller Data Input.

SDIOM

SPI Controller Data Input/Output.

SDOM

SPI Controller Data Output.

SCKM

SPI Controller Clock Output.

SDA

I2C Controller Data Input/Output.

SCL

I2C Controller Clock Output.

The 6-byte COMM register stores all the data and control bits

required for the I2C or SPI communication. It contains up to

three data bytes to be transmitted to or received from the

peripheral device. It also contains three control bytes that

specify whether the bytes are transferred in I2C or in SPI mode

and the control action to be taken prior (ICOM bit fields) and

after (FCOM bit fields) the transaction of the individual bytes.

Table 82. COMM Command Codes

Name

Type

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Description

WRCOMM

WR48

Write COMM register (ADBMS6830B: WRCOMM).

RDCOMM

RD48

Read COMM register (ADBMS6830B: RDCOMM).

STCOMM

CMD

Send COMM register (ADBMS6830B: STCOMM).

Table 83. COMM Register Map

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ICOM0[3:0]

FCOM0[3:0]

D0[7:0]

ICOM1[3:0]

FCOM1[3:0]

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