ADBMS2950BCCSZ datasheet(54/97 Pages) AD

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ADBMS2950B

Data Sheet

Rev. 0 | Page 54 of 97

Name

Type

Reset

Value

Description

GPIO2 controlled by GPIO2C or COMM register.

GPIO2 toggles on end of conversion of OC1ADC.

The VDIV measurement follows the nominal value of VREF1

(which varies between different ICs) according to the specified

VREF1 to VDIV ratio listed in the Table 7.

The FLAG register stores fault and status information and is

read by the RDFLAG command. The CLRFLAG command is

used to reset individual bits in the FLAG register. The data sent

with the CLRFLAG command defines the flag bits to be cleared

(1) and the bits that are not altered (0).

Table 73. FLAG Register Map

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RESERVED

VDRUV

OCMM2

OC3L

OCAGD/CLRM2

OCAL

OC1L

RESERVED

VDDUV2

NOCLK2

REFFLT2

OCBGD2

OCBL

OC2L

I2CNT[2:0]1

I1CNT[10:6]1

I1CNT[5:0]1

I1PHA[1:0]1

VREGOV2

VREGUV2

VDIGOV2

VDIGUV2

SED1

MED12

SED2

MED22

VDEL

VDE2

SPIFLT

RESET3

THSD3, 4

TMODE2

OSCFLT2

Notes:

Bits are read-only and are not controlled by the CLRFLAG

command.

Bits contribute to FAULT output on OCA, OCB and, if

GPIO1FE is set, also on GPIO1. If any of those bits is set, the

output pins are set to the fault state.

Related events cause OCA, OCB, GPIOx, and GPOx to enter

the high-impedance mode.

Not cleared by SRST.

For best independence, the overcurrent-related bits are not

perfectly synchronized with each other and are subject to

slightly different propagation delays. Not all bits in the FLAG

cleared with the CLRFLAG command after the pending fault

condition has been removed.

Table 74. FLAG Bit Description

Name

Type

Reset

Value

Description

OC1L

RW1C,

FRZ

OC1ADC Overcurrent Latch.

No OC1 threshold event passed deglitching.

OC1 threshold event detected and passed deglitching.

OC2L

RW1C,

FRZ

OC2ADC Overcurrent Latch.

No OC2 threshold event passed deglitching.

OC2 threshold event detected and passed deglitching.

OC3L

RW1C,

FRZ

OC3ADC Overcurrent Latch.

No OC3 threshold event passed deglitching.

OC3 threshold event detected and passed deglitching.

REFFLT

RW1C,

FRZ

OC Fault Latch.

No OC Fault.

OC Fault.

OCAL

RW1C,

FRZ

Majority Voter A Overcurrent Latch.

No OC event passed majority Voter A.

OC event detected that passed majority Voter A.

OCBL

RW1C,

FRZ

Majority Voter B Overcurrent Latch.

No OC event passed majority Voter B.

OC event detected that passed majority Voter B.

OCAGD/CLRM

RW1C,

FRZ

OCA Gate/Drain Mismatch Latch. Clear OC3 Min/Max.

OCA output reads back as expected.

Detected unexpected readback from OCA output while OCEN = 1.

Clear operation also clears OC3MIN and OC3MAX registers.

OCBGD

RW1C,

FRZ

OCB Gate/Drain Mismatch Latch.

OCB output reads back as expected.

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