ADBMS2950BCCSZ datasheet(62/97 Pages) AD

62 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 62 of 97

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

D1[7:0]

ICOM2[3:0]

FCOM2[3:0]

D2[7:0]

Table 84. COMM Bit Descriptions

Name

Type

Reset

Value

Write Operation

Read Operation

D0, 1, 2

0x00

Transmit Data Byte 0, 1, 2.

Receive Data Byte 0, 1, 2.

ICOM0, 1, 2

0000

Control action prior transaction of byte D0, D1, D2.

Result of control action.

0000

I2C: BLANK.

I2C: SDA is held low between bytes.

0001

I2C: STOP.

I2C: Controller generated a STOP.

0110

I2C: START.

I2C: Controller generated a START.

0111

I2C: No transmit.

I2C: SDA is held high between bytes.

1000

SPI: Drive CSBM low.

SPI: Always 0111.

1001

SPI: Drive CSBM high, clock and data continues.

1010

SPI: Drive CSBM high, then low.

1111

SPI: No transmit, release outputs, remaining data ignored.

Other

Reserved, undetermined behavior.

FCOM0, 1, 2

0000

Control action after transaction byte D0, D1, D2.

Result of control action.

0000

I2C: Controller ACK on 9th clock.

SPI: Holds CSBM low after byte transmission.

I2C: Controller generated an ACK.

0001

I2C: Peripheral generated an ACK, Controller a STOP.

0111

I2C: Peripheral generated an ACK.

1000

I2C: Controller NACK on 9th clock.

SPI: Holds CSBM low after byte transmission.

1001

I2C: Controller NACK followed by STOP.

SPI: Transitions CSBM high after byte transmission.

I2C: Peripheral generated a NACK, Controller a STOP.

1111

SPI: Read.

I2C: Peripheral generated a NACK.

SPI: Always 1111.

Other

Reserved, undetermined behavior.

The COMM register can be written by the WRCOMM

command and can be read by the RDCOMM command. The

STCOMM command initiates the transfer. The transfer is

clocked by the SCK clock that the ADBMS2950B receives from

its (iso)SPI host. When sending an STCOMM command, the

remote SPI host must extend the same SPI frame by 24 SCK

clock cycles (3 bytes) per data byte without releasing CSB high.

Thus, the host must send STCOMM (4 bytes) followed by 3

bytes to send 1 byte to the serial peripheral. Similar STCOMM

is followed by 6 bytes to transmit 2 bytes and 9 bytes to transmit

3 bytes. The number of bytes after STCOMM is independent of

the length of a daisy-chain, and the data is do not care.

When more than three bytes are to be transferred, multiple

WRCOMM, RDCOMM, and STCOMM commands can be

bundled to transfer groups of up to 3 bytes at a time. An I2C

message is initiated by a START condition and terminated by a

STOP. All intermediate bytes keep the ICOM field in BLANK

state. ACK or NACK can be issued as appropriate. In SPI mode,

a falling edge on CSBM needs to be ensured at the start of a

contiguous message, and the CSBM is held low for the duration

of the message and released high after the last byte.

Assuming that CSB is kept active (Logical Low), and that SCK is

pulsed high (toggle LH and HL) 24 times for each Dn[7:0] (that

is, 72 cycles per WRCOMM and RDCOMM previously set

packet, before CSB can be set to inactive, Logical 1), and

assuming that the timing specification onto the clock phases of

SCK are respected, the timing specifications for the SPI and I2C

controller interfaces are as shown in Figure 44 and Figure 45.

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