ADBMS2950BCCSZ datasheet(48/97 Pages) AD

48 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 48 of 97

Figure 40. PWM1 OCx Assertion with Setting OCDGT = 0, OCDP = 1

Figure 40 shows the typical timings of the sequence WRCFGB,

WRCFGA, and WRCFGA with two ICs in a daisy-chain

showing the OCA, OCB outputs of both ICs.

Even at maximum (iso)SPI clock rate, the time tOCEN,DLY1 is

negative in this scenario and thus the wait time between the two

WRCFGA commands is not required.

To show the effect of the outputs being high impedance when

OCEN is cleared, the IC1 pull-down resistors have been

connected to the OCx pins and the IC2 has been populated

with pull-up resistors.

The duration of the write sequence (tWR) depends on controller

timings such as (iso)SPI clock rate and the number of ICs in a

daisy-chain. The last WRCFGA generating the rising edge of

OCEN starts the interval (tSI = 0.2 ms; nominally 3 to 4

OCxADC conversion cycles) after which the first asserted

(75%) PWM period (tOC = 0.063 ms) starts. Assuming the

external pyrofuse ignition circuitry implementing an off-chip

deglitching only triggers after two consecutively asserted PWM

periods, the total triggering time becomes:

tTOTAL = tWR + tSI + 2 × tOC

The timing plot also shows some more read commands like

RDFLAG, RDSTAT that might be issued after the assertion. The

RDFLAG must especially be issued to validate the OC1L to

OC3L latches being set and the OCAGD, OCBGD bits not

being set. Note that depending on when the RDFLAG is sent, it

might not yet show the OCxL latches being set.

In the shown example, the RDFLAG is sent before the OCx

outputs assert to the 75% PWM signal. In the example, another

RDFLAG issued after the RDSTAT report the OCxL latches

being set.

Table 62. OCxADC Command Codes

Name

Type

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Description

CLRO

CMD

Clears all OCxADC results.

RDOC

RD48

Read OCxADC results (ADBMS6830B: RDCVF).

ADBMS6830B compatible code RDFCF.

Table 63. Overcurrent Return Values

Command

BYTE 5

BYTE 4

BYTE 3

BYTE 2

BYTE 1

BYTE 0

RDOC

OC3MIN

OC3MAX

RESERVED

OC3R

OC2R

OC1R

The CLRO command clears the OCxADC results OC1R to

OC3R. The register values after clearing are shown in Table 64

from OC1R to OC3R, column CLRO. The bit OCAGD/CLRM

of the CLRFLAG command clears the overcurrent min/max

registers OC3MIN and OC3MAX. The register values after

clearing are shown in Table 65 from OC3MAX to OC3MIN,

column CLRM.

Table 64. Overcurrent Result Registers

Name

Type

Reset

CLRO

Description

OC1R

RO, FRZ

0x7F

0x80

Sign-extended 8-bit OC1ADC result register, voltage = OC1R × OC1LSB.

OC2R

RO, FRZ

0x7F

0x80

Sign-extended 8-bit OC2ADC result register, voltage = OC2R × OC2LSB.

OC3R

RO, FRZ

0x7F

0x80

Sign-extended 8-bit OC3ADC result register, voltage = OC3R × OC3LSB.

Table 65. Overcurrent Min/Max Registers

Name

Type

Reset

CLRM

Description

OC3MAX

RO, FRZ

0x7F

0x80

Sign-extended 8-bit OC3ADC conversion maximum, voltage = OC3MAX × OC3LSB.

OC3MIN

RO, FRZ

0x80

0x7F

Sign-extended 8-bit OC3ADC conversion minimum, voltage = OC3MIN × OC3LSB.

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