ADBMS2950BCCSZ datasheet(58/97 Pages) AD

58 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 58 of 97

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OCTSEL

OCDP

OCDGT

OCBX

OCAX

OCMODE

OC3GC

OC2GC

OC1GC

OCOD

GPIO4C

GPIO3C

GPIO2C

GPIO1C

GPIO2EOC

DIAGSEL

GPO6H

GPO5H

GPO4H

GPO3H

GPO2H

GPO1H

GPO6L

GPO5L

GPO4L

GPO3L

GPO2L

GPO1L

GPIO4L

GPIO3L

GPIO2L

GPIO1L

RESERVED

VDRUV

OCMM

OC3L

OCAGD

OCAL

OC1L

RESERVED

VDDUV

NOCLK

REFFLT

OCBGD

OCBL

OC2L

I2CNT2:0

I1CNT10:6

I1CNT5:0

I1PHA[1:0]

VREGOV

VREGUV

VDIGOV

VDIGUV

SED1

MED1

SED2

MED2

VDEL

VDE

SPIFLT

RESET

THSD1

TMODE

OSCFLT

Note:

The thermal shutdown indicator bit THSD is not cleared by

the SRST command, but only after a power-on-reset or through

the CLRFLAG command.

Soft Reset Command

The Soft Reset command (SRST) quickly resets all state

machines and memory registers and initializes all the devices in

the daisy-chain. The Soft Reset command only needs enough

time to propagate up the stack to the next device, after which

the device initializes. After tWAKE, all the ADBMS2950B devices

enter the STANDBY state and are ready to receive new

commands. From the STANDBY state, they automatically

transition to the REFUP state (for more details, see the Core

State Description section).

The host controller must keep log when setting the INJTS bit

for requesting the THSD bit to be asserted. After successfully

reading THSD, the INJTS bit must be cleared via WRCFGA and

the THSD bit must be cleared through CLRFLAG. If a SRST is

issued before clearing THSD, the FLAG register reports RESET

and THSD bits being set, same as if there is a thermal

shutdown. Setting INJTS requests the THSD to be asserted, but

by itself does not trigger an internal reset.

Serial ID

Each ADBMS2950B is programmed at the factory with a

unique 48-bit serial identification code (SID) as a part of the

internal non-volatile memory NVM1. After power-up or reset,

the non-volatile memories are read, and the SID is stored into a

volatile register that can be read through the RDSID command.

Because of the non-redundant implementation, faults in the

SID register cannot be detected.

Snapshot Commands

To enable reading of coherent data from one ADBMS2950B or

several devices in a daisy-chain, the snap command allows

freezing of the continuously updated result registers. After

sending the snap command, the host can read them at

convenience before releasing the freeze by an unsnap

command.

During the freeze, the ADCs continue to measure. Conversions

are accumulated internally to provide IxACC, VBxACC results

together with the latest Ix, VBx results once the unsnap

command is sent. Sending an additional snap command while

the result registers are already frozen does not take a new

snapshot. To trigger a new register update while registers are

frozen, the host must send a sequence of two commands:

unsnap and snap. The CFGA register SNAPST bit indicates the

freeze status.

Upon reception of a snap or unsnap command, the command

counter is incremented. Registers and bits that are subject to the

snap protocol are marked with FRZ in the Type column of the

VB2, I1CNT, I2CNT, and I1PHA registers).

GENERAL-PURPOSE IO PINS

The ADBMS2950B features six GPO pins to fulfill the following

functions:

•

General-purpose static output signals.

•

Control of external high-voltage switches, for example,

MOSFETs, to reduce leakage in high-voltage resistive

dividers when measurement is not needed or to

control the isolation measurement sequences as

shown in the Typical Application section.

•

Control of start-up self-test sequences of external

circuitry.

•

Additional chip-selects where more than one SPI

peripheral must be controlled through the COMM

interface.

The GPOs provide the following features:

•

Set the output state (GPO1C to GPO6C).

•

Configurable open-drain mode or push-pull mode, up

to VDD voltage (GPO1OD to GPO6OD).

•

Dual-threshold readback (GPO1H to GPO6H and

GPO1L to GPO6L).

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