AM62A7 datasheet(141/238 Pages) TI1

141 / 238 page

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

For no extra_delay:

•

GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed

•

GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed

•

GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed

•

GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed

GPMC_CLK

GPMC_CSn[i]

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

Valid Address

D 0

F12

F13

F11

F19

F18

F20

F10

F19

F12

GPMC_01

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 7-46. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)

www.ti.com

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

Submit Document Feedback

141

Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1

AM62A7 датащи(PDF) 141 Page - Texas Instruments

AM62A7 датащи(HTML) 141 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL