AM62A7 datasheet(145/238 Pages) TI1

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7.10.5.11.2 GPMC and NOR Flash — Asynchronous Mode

Table 7-65 and Table 7-66 present timing requirements and switching characteristics for GPMC and NOR Flash

— Asynchronous Mode.

Table 7-65. GPMC and NOR Flash Timing Requirements – Asynchronous Mode

see Figure 7-51, Figure 7-52, Figure 7-53, and Figure 7-55

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX UNIT

FA5

(1)

tacc(d)

Data access time

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(4)

FA2

(2)

tacc1-pgmode(d)

Page mode successive data access time

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(3)

FA2

(1)

tacc2-pgmode(d)

Page mode first data access time

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(4)

(1)

The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active

functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2)

The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3)

P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)

(4)

H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)

(5)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 7-66. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

see Figure 7-51, Figure 7-52, Figure 7-53, Figure 7-54, Figure 7-55, and Figure 7-56

NO.

PARAMETER

DESCRIPTION

MODE

(15)

MIN

MAX

UNIT

133 MHz

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

N (12)

Write

N (12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13)

low

Read

A (1)

Write

A (1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

B - 2 (2)

B + 2(2)

Write

B - 2(2)

B + 2(2)

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

C - 2(3)

C + 2(3)

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2(9)

J + 2(9)

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2(9)

J + 2(9)

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

K - 2(10) K + 2(10)

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

L - 2(11) L + 2(11)

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

G (7)

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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