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AM62A7 датащи(PDF) 140 Page - Texas Instruments

номер детали AM62A7
подробное описание детали  AM62Ax Sitara™ Processors
PDF  238 Pages
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AM62A7 датащи(HTML) 140 Page - Texas Instruments

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•
Case GPMCFCLKDIVIDER = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
–
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
–
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8)
For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
–
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
•
Case GPMCFCLKDIVIDER = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
–
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9)
J = GPMC_FCLK(14)
(10) First transfer only for CLK DIV 1 mode.
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(16) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77A – MARCH 2023 – REVISED AUGUST 2023
www.ti.com
140
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1



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