AM62A7 datasheet(127/238 Pages) TI1

номер детали	AM62A7

подробное описание детали	AM62Ax Sitara™ Processors

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7.10.5.5 DSS

Table 7-42, Table 7-43, Figure 7-35, Table 7-44 and Figure 7-36 present timing conditions, requirements, and

switching characteristics for DSS.

Table 7-42. DSS Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.44

26.4

V/ns

OUTPUT CONDITIONS

Output load capacitance

1.5

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

Table 7-43. DSS External Pixel Clock Timing Requirements

see Figure 7-35

NO.

MIN

MAX

UNIT

tc(extpclkin)

Cycle time, VOUT(x)_EXTPCLKIN(2)

6.06

tw(extpclkinL)

Pulse duration, VOUT(x)_EXTPCLKIN(2) low

0.475P(1)

tw(extpclkinH)

Pulse duration, VOUT(x)_EXTPCLKIN(2) high

0.475P(1)

(1)

P = VOUT(x)_EXTPCLKIN cycle time in ns

(2)

x in VOUT(x) = 0

VOUT(x)_EXTPCLKIN

DPI_TIMING_02

Falling-edge Clock Reference

Rising-edge Clock Reference

VOUT(x)_EXTPCLKIN

Figure 7-35. DSS External Pixel Clock Timing Requirements

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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