AM62A7 datasheet(131/238 Pages) TI1

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7.10.5.7.2 JTAG

Table 7-50. JTAG Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

2.0

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

83.5

1000(1)

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

(1)

Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It

may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the

additional trace delay.

Table 7-51. JTAG Timing Requirements

see Figure 7-40

NO.

MIN

MAX

UNIT

tc(TCK)

Cycle time minimum, TCK

40(1)

tw(TCKH)

Pulse width minimum, TCK high

0.4P(2)

tw(TCKL)

Pulse width minimum, TCK low

0.4P(2)

tsu(TDI-TCK)

Input setup time minimum, TDI valid to TCK high

tsu(TMS-TCK)

Input setup time minimum, TMS valid to TCK high

th(TCK-TDI)

Input hold time minimum, TDI valid from TCK high

th(TCK-TMS)

Input hold time minimum, TMS valid from TCK high

(1)

The maximum TCK operating frequency assumes the following timing requirements and switching characteristis for the attached

debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these

assumptions.

•

Minimum TDO setup time of 2 ns relative to the rising edge of TCK

•

TDI and TMS output delay in the range of -12.9 ns to 13.9 ns relative to the falling edge of TCK

(2)

P = TCK cycle time in ns

Table 7-52. JTAG Switching Characteristics

see Figure 7-40

NO.

PARAMETER

MIN

MAX

UNIT

td(TCKL-TDOI)

Delay time minimum, TCK low to TDO invalid

td(TCKL-TDOV)

Delay time maximum, TCK low to TDO valid

TDO

TCK

TDI / TMS

Figure 7-40. JTAG Timing Requirements and Switching Characteristics

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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