AM62A7 datasheet(124/238 Pages) TI1

номер детали	AM62A7

подробное описание детали	AM62Ax Sitara™ Processors

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7.10.5.2 CPTS

Table 7-38, Table 7-39, Figure 7-32, Table 7-40, and Figure 7-33 present timing conditions, requirements, and

switching characteristics for CPTS.

Table 7-38. CPTS Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

Table 7-39. CPTS Timing Requirements

see Figure 7-32

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(HWTSPUSHH)

Pulse duration, HWnTSPUSH high

12P(1) + 2

tw(HWTSPUSHL)

Pulse duration, HWnTSPUSH low

12P(1) + 2

tc(RFT_CLK)

Cycle time, RFT_CLK

tw(RFT_CLKH)

Pulse duration, RFT_CLK high

0.45T(2)

tw(RFT_CLKL)

Pulse duration, RFT_CLK low

0.45T(2)

(1)

P = functional clock period in ns.

(2)

T = RFT_CLK cycle time in ns.

RFT_CLK

HWn_TSPUSH

Figure 7-32. CPTS Timing Requirements

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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