VT8235 datasheet(92/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-86-

I/O Space Power Management Registers

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I/O Offset 2D-2C - Global Control...................................RW

15-12 Reserved

........................................ always reads 0

IDE Secondary Bus Power-Off

Disable .................................................. default

Enable

IDE Primary Bus Power-Off

Disable .................................................. default

Enable

Reserved

........................................ always reads 0

SMI Active

SMI Inactive.......................................... default

SMI Active. If the SMI Lock bit is set, this bit

needs to be written with a 1 to clear it before

the next SMI can be generated.

LID Triggering Polarity

Rising Edge ........................................... default

Falling Edge

THRM# Triggering Polarity

Rising Edge ........................................... default

Falling Edge

Battery Low Resume Disable

Enable resume ....................................... default

Disable

resume

from

suspend

when

BATLOW# is asserted

4-3

Reserved

........................................ always reads 0

Power Button Triggering Select

SCI/SMI generated by PWRBTN# rising edge

.................................................... default

SCI/SMI generated by PWRBTN# falling

edge

Set to zero to avoid the situation where the Power

Button Status bit is set to wake up the system then

reset again by PBOR Status to switch the system into

the soft-off state.

BIOS Release

This bit is set by legacy software to indicate release

of the SCI/SMI lock.

Upon setting of this bit,

hardware automatically sets the Global Status bit.

This bit is cleared by hardware when the Global

Status bit cleared by software.

Note that if the Global Enable bit is set (Power

Management Enable register Rx2[5]), then setting

this bit causes an SCI to be generated (because

setting this bit causes the Global Status bit to be set).

SMI Enable

Disable all SMI generation.................... default

Enable SMI generation

I/O Offset 2F - SMI Command ........................................ RW

7-0

SMI Command

Writing to this port sets the Software SMI Status bit.

Note that if the Software SMI Enable bit is set (see

Global Enable register Rx2A[6]), then an SMI is

generated.

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