VT8235 datasheet(49/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

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Memory Mapped I/O APIC Registers

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Memory Mapped I/O APIC Registers

Memory Address FEC00000 – APIC Index ....................RW

7-0

APIC Index

.......................................... default = 00h

8-bit pointer to APIC registers.

Memory Address FEC00013-10 – APIC Data ................RW

31-0 APIC Data

............................. default = 0000 0000h

Data for the APIC register pointed to by the APIC

index

Memory Address FEC00020 – APIC IRQ Pin AssertionWO

7-5

Reserved

........................................ always reads 0

4-0

APIC IRQ Number

........................default undefined

IRQ # for this interrupt. Valid values are 0-23 only.

Memory Address FEC00040 – APIC EOI ..................... WO

7-0

Redirection Entry Clear

................default undefined

When a write is issued to this register, the APIC will

check this field and compare it with the vector field

for each entry in the I/O redirection table. When a

match is found, the “Remote_IRR” bit for that I/O

Redirection Entry will be cleared.

Indexed I/O APIC Registers

Offset 0 – APIC Identification (0000 0000h) .................. RW

31-28 Reserved

........................................always reads 0

27-24 APIC Identification

..................................default = 0

Software must program this value before using the

APIC.

23-0 Reserved

........................................always reads 0

Offset 1 – APIC Version (00178003) ................................ RO

31-24 Reserved

....................................always reads 00h

23-16 Maximum Redirection

...................always reads 17h

Equal to the number of APIC interrupt pins minus

one. For this APIC, this value is 17h (23 decimal).

PCI IRQ

Always reads 1 to indicate that the IRQ assertion

allowed to write to it to cause interrupts.

14-8 Reserved

........................................always reads 0

7-0

APIC Version

..................................always reads 03h

The implementation version for this APIC is 03h.

Offset 2 – APIC Arbitration (0000 0000h)....................... RO

31-28 Reserved

....................................always reads 00h

27-24 APIC Arbitration ID

......................always reads 00h

23-0 Reserved

....................................always reads 00h

Offset 3 – Boot Configuration (0000 0000h) ................... RW

31-1 Reserved

....................................always reads 00h

Interrupt Delivery Mechanism

APIC Serial Bus..................................... default

Front Side Bus Message

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