VT8235 datasheet(89/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-83-

I/O Space Power Management Registers

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Processor Power Management Registers

I/O Offset 13-10 - Processor & PCI Bus Control............RW

31-12 Reserved

........................................ always reads 0

Disable PCISTP# When PCKRUN# is Deasserted

Enable.................................................... default

Disable

PCI Bus Clock Run Without Stop

PCKRUN# is always asserted ............... default

PCKRUN# will be de-activated after the PCI

bus is idle for 26 clocks

Host Clock Stop

This bit controls whether CPUSTP# is asserted in C3

and S1 states. Normally CPUSTP# is not asserted in

C3 and S1 states, only STPCLK# is asserted.

CPUSTP# will not be asserted in C3 and S1

states (only STPCLK# is asserted) ........ default

CPUSTP# will be asserted in C3 and S1 states

Assert SLP# for Processor Level 3 Read

This bit controls whether SLP# is asserted in C3

state.

SLP# is not asserted in C3 state ............ default

SLP# is asserted in C3 state

Used with Intel CPUs only.

Lower CPU Voltage During C3 / S1

This bit controls whether the CPU voltage is lowered

when in C3/S1 state. The voltage is lowered using

the VRDSLP signal to the voltage regulator. PMIO

RxE5[3] must be 0 to enable the voltage change

function. Bits 8 and 9 of this register must also be set

to 1.

Disable (normal voltage during C3/S1)....... def

Enable (lower voltage during C3/S1)

6-5

Reserved

........................................ always reads 0

Throttling Enable

Setting this bit starts clock throttling (modulating the

STPCLK# signal) regardless of the CPU state. The

throttling duty cycle is determined by bits 3-0 of this

3-0

Throttling Duty Cycle

This field determines the duty cycle of the STPCLK#

signal when the system is in throttling mode

("Throttling Enable" bit set to one). The duty cycle

indicates the percentage of performance (the lower

the percentage, the lower the performance and the

higher the power savings).

0000 Reserved

0001 0-6.25%

0010 6.25-12.50%

0011 18.75-25.00%

0100 31.25-37.50%

0101 37.50-43.75%

0110 43.75-50.00%

0111 50.00-56.25%

1000 56.25-62.50%

1001 62.50-68.75%

1010 68.75-75.00%

1011 75.00-87.50%

1100 75.00-81.25%

1101 81.25-87.50%

1110 87.50-93.75%

1111 93.75-100%

I/O Offset 14 - Processor Level 2 ...................................... RO

7-0

Level 2

........................................always reads 0

Reads from this register put the processor into the

Stop Grant state (the VT8235 asserts STPCLK# to

suspend the processor). Wake up from Stop Grant

state is by interrupt (INTR, SMI, and SCI).

Reads from this register return all zeros; writes to this register

have no effect.

I/O Offset 15 - Processor Level 3 ...................................... RO

7-0

Level 3

........................................always reads 0

Reads from this register put the processor in the C3

clock state with the STPCLK# signal asserted.

Rx10[9] = 1 then the CPU clock is also stopped by

asserting CPUSTP#. Wakeup from the C3 state is by

interrupt (INTR, SMI, and SCI).

Reads from this register return all zeros; writes to this register

have no effect.

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