VT8235 datasheet(42/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-36-

Legacy I/O Registers

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Legacy I/O Ports

This group of registers includes the DMA Controllers,

Interrupt Controllers, and Timer/Counters as well as a number

of miscellaneous ports originally implemented using discrete

logic on original PC/AT motherboards. All of the registers

listed are integrated on-chip. These registers are implemented

in a precise manner for backwards compatibility with previous

generations of PC hardware.

These registers are listed for

information purposes only.

Detailed descriptions of the

actions and programming of these registers are included in

numerous

industry

publications

(duplication

that

information here is beyond the scope of this document). All

of these registers reside in I/O space.

Port 61 - Misc Functions & Speaker Control ................. RW

7-6

Reserved

........................................always reads 0

Timer/Counter 2 Output

......................................RO

This bit reflects the output of Timer/Counter 2

without any synchronization.

Refresh Detected

...................................................RO

This bit toggles on every rising edge of the ISA bus

REFRESH# signal.

3-2

Reserved

....................................... RW, default=0

Speaker Enable

....................................................RW

Disable ................................................... default

Enable Timer/Ctr 2 output to drive SPKR pin

Timer/Counter 2 Enable

.....................................RW

Disable ................................................... default

Enable Timer/Counter 2

Port 92h - System Control................................................ RW

7-6

Hard Disk Activity LED Status

Off

.................................................... default

1-3 On

5-4

Reserved

........................................always reads 0

Power-On Password Bytes Inaccessable

...default=0

Reserved

........................................always reads 0

A20 Address Line Enable

A20 disabled / forced 0 (real mode) ...... default

A20 address line enabled

High Speed Reset

Normal

Briefly pulse system reset to switch from

protected mode to real mode

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