VT8235 datasheet(83/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-77-

Device 17 Function 0 Power Management Registers

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Offset 94 – Power Well Control ...................................... WO

SMBus Clock Select

SMBus Clock from 14.31818 MHz Divider

SMBus Clock from RTC 32.768 KHz ... defult

Reserved

........................................ always reads 0

Internal PLL Reset During Suspend

Enable.................................................... default

Disable

SUSST1# / GPO3 Select (Pin Y3)

SUSST1#............................................... default

GPO3

GPO2 / SUSB# Select (Pin AF2)

SUSB#................................................... default

GPO2

GPO1 / SUSA# Select (Pin AA2)

SUSA# .................................................. default

GPO1

1-0

GPO0 Output Select (Pin AA3)

This field controls the GPO0 output signal for Pulse

Width Modulation.

00 GPO0 Fixed Output Level (defined by PMIO

Rx4C[0]) ............................................... default

01 GPO0 output is 1 Hz “SLOWCLK”

10 GPO0 output is 4 Hz “SLOWCLK”

11 GPO0 output is 16 Hz “SLOWCLK”

Offset 95 – Miscellaneous Power Well Control .............. RW

CPUSTP# to SUSST# Delay Select

This bit controls the delay between the deassertion of

CPUSTP# and the deassertion of SUSST# during a

resume.

1 msec minimum ................................... default

125 usec minimum

SUSST# Deasserted Before PWRGD for STD

Disable ................................................... default

Enable (SUST# is deasserted before PWRGD

when resuming from STD)

Keyboard / Mouse Port Swap

This bit determines whether the keyboard and mouse

ports can be swapped.

Disable ................................................... default

Enable

Reserved

........................................always reads 0

SMB2 / GPO Select

SMBDT2 / SMBCK2 ............................ default

GPO26 / GPO27

AOL 2 SMB Slave

This bit controls whether external SMB masters can

access internal SMB registers (for Alert-On-LAN).

Enable (external SMB masters may reset /

resume the system (when Rx96[4]=1) or detect

GPI status) ............................................. default

Disable

SUSCLK / GPO4 Select

SUSCLK................................................ default

GPO4

USB Wakeup for STR / STD / SoftOff

This bit controls whether USB Wakeup is enabled

when PMIO Rx21-20[14] (USB Wakeup Status) = 1.

This allows wakeup from STR, STD, Soft Off, and

POS.

Disable ................................................... default

Enable

Offset 96 – Power On / Reset Control ............................. RW

7-4

Reserved

........................................always reads 0

3-0

CPU Frequency Strapping Value Output to NMI,

INTR, IGNNE#, and A20M# during RESET#

The value written to this field is strapped through

NMI, INTR, IGNNE#, and A20M# during RESET#

to determine the multiplier for setting the CPU’s

internal frequency.

If the CPU hangs due to

inappropriate settings written here, the GP3 timer

(second timeout) can be used to initiate a system

reboot (PMIO Rx42[2] = 1).

Refer to the BIOS

Porting Guide for additional details.

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