VT8235 datasheet(46/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-40-

Legacy I/O Registers

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Interrupt Controller I/O Registers

Ports 20-21 - Master Interrupt Controller

The Master Interrupt Controller controls system interrupt

channels 0-7.

Two registers control the Master Interrupt

Controller. They are:

I/O Address Bits 15-0

0000 0000 001x xxx0

Master Interrupt Control

0000 0000 001x xxx1

Master Interrupt Mask

Note that not all bits of the address are decoded.

The Master Interrupt Controller is compatible with the Intel

8259 Interrupt Controller chip. Detailed descriptions of 8259

Interrupt Controller operation can be obtained from the Intel

Peripheral Components Data Book and numerous other

industry publications.

Ports A0-A1 - Slave Interrupt Controller

The Slave Interrupt Controller controls system interrupt

channels 8-15.

The slave system interrupt controller also

occupies two register locations:

I/O Address Bits 15-0

0000 0000 101x xxx0

Slave Interrupt Control

0000 0000 101x xxx1

Slave Interrupt Mask

Note that not all address bits are decoded.

The Slave Interrupt Controller is compatible with the Intel

8259 Interrupt Controller chip. Detailed descriptions of 8259

Interrupt Controller operation can be obtained from the Intel

Peripheral Components Data Book and numerous other

industry publications.

Interrupt Controller Shadow Registers

The following shadow registers are enabled by setting

function 0 Rx47[4]. If the shadow registers are enabled, they

are read back at the indicated I/O port instead of the standard

interrupt controller registers (writes are unchanged).

Port 20 - Master Interrupt Control Shadow ................... RO

Port A0 - Slave Interrupt Control Shadow...................... RO

Reserved

........................................always reads 0

OCW3 bit 2 (POLL)

OCW3 bit 0 (RIS)

OCW3 bit 5 (SMM)

OCW2 bit 7 (R)

ICW4 bit 4 (SFNM)

ICW4 bit 1 (AEOI)

ICW1 bit 3 (LTIM)

Port 21 - Master Interrupt Mask Shadow ....................... RO

Port A1 - Slave Interrupt Mask Shadow ........................ RO

7-5

Reserved

........................................always reads 0

4-0

T7-T3 of Interrupt Vector Address

Timer / Counter Registers

Ports 40-43 - Timer / Counter I/O Registers

There are 4 Timer / Counter registers:

I/O Address Bits 15-0

0000 0000 010x xx00

Timer / Counter 0 Count

0000 0000 010x xx01

Timer / Counter 1 Count

0000 0000 010x xx10

Timer / Counter 2 Count

0000 0000 010x xx11

Timer / Counter Cmd Mode

Note that not all bits of the address are decoded.

The Timer / Counters are compatible with the Intel 8254

Timer / Counter chip. Detailed descriptions of 8254 Timer /

Counter operation can be obtained from the Intel Peripheral

Components

Data

Book

and

numerous

other

industry

publications.

Timer / Counter Shadow Registers

The following shadow registers are enabled for readback by

setting function 0 Rx47[4].

If the shadow registers are

enabled, they are read back at the indicated I/O port instead of

the standard timer / counter registers (writes are unchanged).

Port 40 – Counter 0 Base Count Value (LSB 1

st MSB 2nd)RO

Port 41 – Counter 1 Base Count Value (LSB 1

st MSB 2nd)RO

Port 42 – Counter 2 Base Count Value (LSB 1

st MSB 2nd)RO

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