VT8235 datasheet(87/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-81-

I/O Space Power Management Registers

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Power Management I/O-Space Registers

Basic Power Management Control and Status

I/O Offset 1-0 - Power Management Status .................RWC

The bits in this register are set only by hardware and can be

reset by software by writing a one to the desired bit position.

Wakeup Status

......................................... default = 0

This bit is set when the system is in the suspend state

and an enabled resume event occurs. Upon setting

this bit, the system automatically transitions from the

suspend state to the normal working state (from C3 to

C0 for the processor).

14-12 Reserved

........................................ always reads 0

Abnormal Power-Off Status

................... default = 0

RTC Alarm Status

................................... default = 0

This bit is set when the RTC generates an alarm (on

assertion of the RTC IRQ signal).

Sleep Button Status

.................................. default = 0

This bit is set when the sleep button is pressed

(SLPBTN# signal asserted low).

Power Button Status

................................ default = 0

This bit is set when the PWRBTN# signal is asserted

low. If the PWRBTN# signal is held low for more

than four seconds, this bit is cleared, the Power

Button Status bit is set, and the system will transition

into the soft off state.

7-6

Reserved

........................................ always reads 0

Global Status

............................................ default = 0

This bit is set by hardware when the BIOS Release

bit is set (typically by an SMI routine to release

control of the SCI / SMI lock).

When this bit is

cleared by software (by writing a one to this bit

position) the BIOS Release bit is also cleared at the

same time by hardware.

Bus Master Status

.................................... default = 0

This bit is set when a system bus master requests the

system bus.

All PCI master, ISA master and ISA

DMA devices are included.

3-1

Reserved

........................................ always reads 0

ACPI Timer Carry Status

....................... default = 0

The bit is set when the 23

rd (31st) bit of the 24 (32)

bit ACPI power management timer changes.

I/O Offset 3-2 - Power Management Enable .................. RW

The bits in this register correspond to the bits in the Power

Management Status Register at offset 1-0.

Reserved

........................................always reads 0

14-12 Reserved

........................................always reads 0

Reserved

........................................always reads 0

RTC Alarm Enable

..................................default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI Enable bit) to be

generated when the RTC Status bit is set.

Sleep Button Enable

.................................default = 0

This bit may be set to trigger either an SCI or SMI

when the Sleep Button Status bit is set.

Power Button Enable

...............................default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI Enable bit) to be

generated when the Power Button Status bit is set.

7-6

Reserved

........................................always reads 0

Global Enable

...........................................default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI Enable bit) to be

generated when the Global Status bit is set.

Reserved

........................................always reads 0

3-1

Reserved

........................................always reads 0

ACPI Timer Enable

..................................default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI Enable bit) to be

generated when the Timer Status bit is set.

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