VT8235 datasheet(86/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-80-

Device 17 Function 0 Power Management Registers

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General Purpose I/O Control Registers

Offset E0 – GPI Inversion Control ..................................RW

7-0

GPI[27-24, 19-16] Input Inversion

Non-inverted input ................................ default

Inverted input

Offset E1 – GPI SCI / SMI Select.....................................RW

7-0

GPI[27-24, 19-16] SCI / SMI Select

When GPI[27-24,19-16] are set to enable SCI / SMI

generation (PMIO Rx52), this field determines

whether an SCI or SMI is generated.

SCI

.................................................... default

SMI

Offset E4 – GPO Pin Select ..............................................RW

Reserved

........................................ always reads 0

ACSDIN2,3 / GPIO20,21 Select (Pins U2, V1)

This bit is ignored if any of RxE5 bits 1, 2, 4, or 5 = 1

U2 = ACSDIN2, V1 = ACSDIN3 ......... default

U2 = GPIO20, V1 = GPIO21

SA[19:16] / GPO[19:16] Select (AC11, AD11,

AE11, AF11)

SA[19:16].............................................. default

GPO[19:16]

GPIO[15:12] Direction

Input (pins are GPI[15:12]) ................... default

Output (pins are GPO[15:12])

GPIO[11:8] Direction

Input (pins are GPI[11:8]) ..................... default

Output (pins are GPO[11:8])

GNT5# / GPO7 Select (Pin P4)

REQ5# / GPI7 Select (Pin N4)

P4 = GPO7, N4 = GPI7......................... default

P4 = GNT5#, N4 = REQ5#

PCISTP# / GPO6 Select (Pin AF6)

V6 = PCISTP#....................................... default

V6 = GPO6

CPUSTP# / GPO5 Select (Pin AC7)

Y5 = CPUSTP# ..................................... default

Y5 = GPO5

Offset E5 – GPIO I/O Select 1 ......................................... RW

Voltage Regulator Change Timer Select

100 usec ................................................. default

200 usec

AGPBZ# Source of Bus Master Status

Disable ................................................... default

Enable

Reserved

........................................always reads 0

VGATE on GPIO8 (Pin C8)

U2 = GPIO8........................................... default

U2 = VGATE (bit 1 and RxE4[6] are ignored)

CPU Frequency Change

Enable .................................................... default

Disable

PCS1# on ACSDIN3 (Pin V1)

V1 = ACSDIN3 / GPIO21 / SLPBTN# . default

V1 = PCS1# (RxE4[6] ignored)

PCS0# on ACSDIN2 (Pin U2)

U2 = ACSDIN2 / GPIO20..................... default

U2 = PCS0# (RxE4[6] ignored)

IORDY / GPI19 Select (Pin AD10)

AD10 = IORDY..................................... default

AD10 = GPI19

Offset E6 – GPIO I/O Select 2 ......................................... RW

GPI31 / GPO31 (GPIOE) Select (Pin AC6)

AC6 = GPI31 ......................................... default

AC6 = GPO31 / GPIOE

GPI30 / GPO30 (GPIOD) Select (Pin AD6)

AD6 = GPI30......................................... default

AD6 = GPO30 / GPIOD

5-2

Reserved

........................................always reads 0

GPI25 / GPO25 (GPIOC) Select (Pin AE6)

AE6 = GPI25 ......................................... default

AE6 = GPO25 / GPIOC

GPI24 / GPO24 (GPIOA) Select (Pin AE5)

AE5 = GPI24 ......................................... default

AE5 = GPO24 / GPIOA

Offset E7 – GPO Output Type......................................... RW

These bits determine whether the indicated GPO pin is open

drain or TTL when the corresponding bit of RxE6 = 1.

GPO31 OD/TTL Select (Pin AC6)

GPO30 OD/TTL Select (Pin AD6)

5-2

Reserved

........................................always reads 0

GPO25 OD/TTL Select (Pin AE6)

GPO24 OD/TTL Select (Pin AE5)

For all defined bits above:

.................................................... default

TTL

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