UPD360 datasheet(153/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 153

UPD360

11.4.3

PD MAC INTERRUPT STATUS AND ENABLE REGISTERS

The following sub-sections describe the various registers associated with the PD MAC interrupts.

Refer to Section 8.1, "System Interrupts," on page 35 for additional information on system level interrupt control.

11.4.3.1

MAC Interrupt Status Register (MAC_IRQ_STAT)

This register reflects the summary status of the various interrupt sources. If any of these bits are set, the MAC_INT inter-

rupt bit in the Interrupt Status Register (INT_STS) will be active (if enabled).

Bits in this register are read only and reflect the combined result of the other PD MAC interrupt status registers.

There is no corresponding enable register, since all interrupts have enables at lower levels of the hierarchy.

Address:

1A80h

Size:

8 bits

Bits

Description

Type

Default

7:5

RESERVED

RX_SOP_IRQ_STAT

RX SOP status. This bit is set when any bit in the RX SOP Interrupt Status

Enable Register (RX_SOP_IRQ_EN).

This bit can only be cleared by clearing or disabling the bit(s) in the RX SOP

Interrupt Status Register (RX_SOP_IRQ_STAT).

PM_IRQ_STAT

Power Management status. This bit is set when any bit in the Power Manage-

ment Interrupt Status Register (PM_IRQ_STAT) is set and enabled via the

Power Management Interrupt Enable and Control Register (PM_IRQ_EN).

This bit can only be cleared by clearing or disabling the bit(s) in the Power

Management Interrupt Status Register (PM_IRQ_STAT).

RX_ERR_IRQ_STAT

RX Error status. This bit is set when any bit in the RX Error Interrupt Status

Enable Register (RX_ERR_IRQ_EN).

This bit can only be cleared by clearing or disabling the bit(s) in the RX Error

Interrupt Status Register (RX_ERR_IRQ_STAT).

RX_IRQ_STAT

RX status. This bit is set when any bit in the RX Interrupt Status Register

(RX_IRQ_STAT) is set and enabled via the RX Interrupt Enable Register

(RX_IRQ_EN).

This bit can only be cleared by clearing or disabling the bit(s) in the RX Inter-

rupt Status Register (RX_IRQ_STAT).

TX_IRQ_STAT

TX status. This bit is set when any bit in the TX Interrupt Status Register

(TX_IRQ_STAT) is set and enabled via the TX Interrupt Enable Register

(TX_IRQ_EN).

This bit can only be cleared by clearing or disabling the bit(s) in the TX Inter-

rupt Status Register (TX_IRQ_STAT).

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