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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPD360 датащи(PDF) 149 Page - Microchip Technology |
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UPD360 датащи(HTML) 149 Page - Microchip Technology |
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149 / 221 page  2016-2017 Microchip Technology Inc. DS00002084C-page 149 UPD360 11.4.2.15 RX FIFO Read Pointer Register (RX_FIFO_RD_PTR) This register contains the RX FIFO read pointer. Software may update this register to flush a packet based on the known packet length and starting point. Software must keep the RX FIFO Read Pointer Control Bits Register coherent with this register if software were to update this register. In order to maintain coherency, writes to this register are held in a temporary register and are transferred to the actual register when the RX FIFO Read Pointer Control Bits Register is written. 11.4.2.16 RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS) This register contains the auxiliary control bits of the RX FIFO read pointer. Software must keep these bits coherent with the RX FIFO Read Pointer if software were to update the latter. Address: 1A50h Size: 8 bits Bits Description Type Default 7 RESERVED RO - 6:0 RX_FIFO_RD_PTR This field contains the RX FIFO read pointer. R/W 0000000b Address: 1A51h Size: 8 bits Bits Description Type Default 7 RX_FIFO_EMPTY This field indicates that the RX FIFO is empty (RX FIFO Write Head Pointer equals the RX FIFO Read Pointer.) RO 1b 6:2 RESERVED RO - 1 RX_FIFO_RD_PTR_AT_TOP This field indicates that the RX FIFO read pointer is at the top of the RAM (location 127). RO 0b 0 RX_FIFO_RX_PTR_WRAP This field toggles each time the RX FIFO read pointer wraps past the top of the RAM (location 127). If software updates the RX FIFO read pointer such that it wraps, this bit must be toggled. R/W 0b |
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