UPD360 datasheet(151/221 Pages) MICROCHIP

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DS00002084C-page 151

UPD360

11.4.2.19

RX FIFO Write Head Pointer Register (RX_FIFO_WR_HEAD_PTR)

This register contains the RX FIFO write head pointer. This pointer indicates where the next received packet starts. This

Software must maintain coherency between this and the other Write Pointer Registers.

There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.

It is assumed that this register is only written while there is no active receive.

11.4.2.20

RX FIFO Write Head Pointer Control Bits Register (RX_FIFO_WR_HEAD_PTR_CTL_BITS)

This register contains the auxiliary control bits of the RX FIFO write head pointer. This register is for debug and test

purpose only and should not normally be written.

Software must maintain coherency between this and the other Write Pointer Registers.

There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.

It is assumed that this register is only written while there is no active receive.

Address:

1A54h

Size:

8 bits

Bits

Description

Type

Default

RESERVED

6:0

RX_FIFO_WR_HEAD_PTR

This field contains the RX FIFO write head pointer.

R/W

0000000b

Address:

1A55h

Size:

8 bits

Bits

Description

Type

Default

RX_FIFO_NO_ROOM_FOR_HEADER

This field indicates that the RX FIFO has no space for the RX header (status

and length) (RX FIFO Write Head Pointer equals the RX FIFO Read Pointer

or RX FIFO Write Head Pointer Plus One equals the RX FIFO Read Pointer).

6:3

RESERVED

RX_FIFO_WR_HEAD_PTR_AT_2ND_FROM _TOP

This field indicates that the RX FIFO write head pointer is one below the top of

the RAM (location 126).

RX_FIFO_WR_HEAD_PTR_AT_TOP

This field indicates that the RX FIFO write head pointer is at the top of the

RAM (location 127).

RX_FIFO_WR_HEAD_PTR_WRAP

This field toggles each time the RX FIFO write head pointer wraps past the top

of the RAM (location 127).

R/W

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