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UPD360 датащи(PDF) 154 Page - Microchip Technology |
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UPD360 датащи(HTML) 154 Page - Microchip Technology |
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154 / 221 page ![]() UPD360 DS00002084C-page 154 2016-2017 Microchip Technology Inc. 11.4.3.2 TX Interrupt Status Register (TX_IRQ_STAT) This register reflects the status of various TX_IRQ_STAT sources. Whether an interrupt is generated or not depends on the values in the TX Interrupt Enable Register (TX_IRQ_EN). Bits in this register are set by hardware and must be cleared by software. Address: 1A81h Size: 8 bits Bits Description Type Default 7 AUTO_RSP_ABORTED A TX auto-response message was aborted. Reason for why the TX was aborted may be determined by reading the TX Auto-Response Abort Status Register (TX_AR_ABORT_STAT). R/W1C 0b 6 AUTO_RSP_SENT Hardware has sent an auto-response. This bit is set when hardware is fin- ished sending an auto-response. R/W1C 0b 5 OK_TO_TX It is now OK to transmit. This bit is set when OK_TO_TX bit in TX Control Register B (TX_CTL_B) changes from 0 to 1 indicating that it is OK for soft- ware to initiate transmission. R/W1C 1b 4 CRC_RCV_TIMEOUT CRC Receive Timer expired. This is a TX failure. This interrupt should be enabled only when Automatic Retry Mode is disabled. The EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A) must be set to enable the timer for use by software. Note: CRC Receive Timer is also used in BIST Mode to time reception of BIST Error Count message. R/W1C 0b 3 TX_EOP Hardware is done sending a packet. Note this does not mean that a valid EOP framing symbol was sent. It only means that packet transmission ended, i.e., transmitter was turned off. This bit set after each TX attempt. This can be used to signal when a Hard or Cable Reset is finished transmis- sion since it does not have a GoodCRC response so the TX_DONE bit will not be set - or if Auto Retry Mode is disabled in which case the hardware is done when the transmitter turns off. This bit is used by software to trigger internal timers. Software must be care- fully when it enables/disables this interrupt because this bit is set after each TX completion. R/W1C 0b 2 TX_ABORTED A TX message was aborted. Reason for why the TX was aborted may be determined by reading the TX Abort Status Register (TX_ABORT_STAT). R/W1C 0b |
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