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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPD360 датащи(PDF) 146 Page - Microchip Technology |
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UPD360 датащи(HTML) 146 Page - Microchip Technology |
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146 / 221 page  UPD360 DS00002084C-page 146 2016-2017 Microchip Technology Inc. 11.4.2.7 RX tReceive Time Register (RX_TRECEIVE_TIME) 11.4.2.8 RX BadCRC Packet Count Register (RX_BADCRC_PKT_CNT) This register keeps track of the number of packets received with bad CRC (any packet with valid SOP but bad CRC or invalid EOP or symbol error). This register is for debug purpose only. If enabled, an interrupt can be generated when the count of this register reaches 128. Address: 1A46h Size: 8 bits Bits Description Type Default 7:0 TRECEIVE CRCReceiveTimer timeout value (tReceive) in 10's of micro seconds. Timeout value = field value * 10 (us) Range: 0-255, specification: 900-1100us (90-110) Note: A value of 0 is invalid and hardware does not check for validity. Note: Hardware uses a free running 1us pulse generator, thus, this CRCReceiveTimer may be 1us less than that expected. Note: Reset value is programmed to be 1000us (+/- 2%). R/W 64h Address: 1A47h Size: 8 bits Bits Description Type Default 7:0 BADCRC_PKT_CNT Number of bad packets received, i.e., with Bad CRC or invalid EOP or symbol error. When the value of this register becomes greater than 127, the DBG_EVENT bit in the RX Interrupt Status Register (RX_IRQ_STAT) will be set. Any write to this register will clear all bits. Note: This register is not affected by packets received during BIST Receiver Test. All these packets will be corrupted. R/WAC 00h |
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