UPD360 datasheet(116/221 Pages) MICROCHIP

116 / 221 page

UPD360

DS00002084C-page 116

 2016-2017 Microchip Technology Inc.

The number of preamble bits sent is programmable by the value of the PREAMBLE_LEN bit in the TX Parameters Reg-

ister B (TX_PARAM_B).

11.1.3.2

TX CRC32

The transmit CRC is reset at the start of transmission (setting of the GO bit in the TX Control Register B (TX_CTL_B)

or by triggering of automatic response by hardware).

The coded nibble data is streamed into the TX CRC32 one nibble at a time for CRC calculation. Only valid D-Code data

is used in CRC calculation. All framing data (invalid D-Code) is excluded from CRC calculation.

11.1.3.3

TX Bit Timing

The baseband transmit signal bit time is controlled by the value in the TX Bit-Time Count Register (TX_BITTIME_CNT).

This value determines the transmit data rate.

The count value is based on clock frequency and is given by:

((Clock Freq KHz / Bit Rate Kbps) - 1)

For example:

Clock Frequency = 48000KHz (48MHz)

Nominal Bit Rate = 300 Kbps

bit_time_cnt = (48000 / 300) - 1 = 159

11.1.4

AUTOMATIC RESPONSE MODE

The device supports an Automatic Response Mode (not to be confused with automatic-data processing mode). In this

mode, the device will automatically send a GoodCRC message upon successful packet reception, or a BIST Error Count

message upon reception of a BIST PRBS frame. This mode can be enabled by setting the EN_AUTO_RSP_MODE bit

in the TX Control Register A (TX_CTL_A).

During normal auto-response, if the bus if found to be busy when the device attempts to send the auto-response (should

not happen, except if there is noise) it will abort the transmission and the AUTO_RSP_ABORTED bit in the TX Interrupt

Status Register (TX_IRQ_STAT) will be set. This behavior can be altered by setting the WAIT4LINE_IDLE bit in the TX

Control Register A (TX_CTL_A). Setting this bit will force the device to wait until the bus becomes idle (refer to the

WAIT4LINE_IDLE bit description for additional information). GoodCRCs and BIST Error Count messages are not retried

even if RETRY_ON_LINE_BUSY in TX_CTL_A is set.

In USB Power Delivery Revision 1.0, Soft Reset had a one-strike rule and failure of Soft Reset led to Hard Reset, leading

to the link being brought down, therefore the transmission of GoodCRC ACK in response to reception of Soft Reset is

handled a little differently. If hardware finds that the line is busy when it attempts to send the GoodCRC ACK it will wait

until the line becomes idle and then re-try the transmission. This process will happen indefinitely. This behavior is same

as what happens to normal GoodCRC ACK when WAIT4LINE_IDLE bit is set. GoodCRCs are not retried even if the

RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) is set. For USB Power Delivery Revision 3.0,

Soft Resets are normally retried, therefore this function should be disabled via the DIS_SPCL_SR_GCRC_ACK bit.

The SOP type that is used for the automatically sent GoodCRC packet is the SOP type of the received packet (parsed

by the receiver). The SOP type that is used for the BIST Error Count message, is selected via the TX_SOP_SELECT

bit in the TX Parameters Register A (TX_PARAM_A).

For both GoodCRC and BIST Error Count messages, bit 8 in the packet header is taken from either the PORT_POW-

ER_ROLE (for SOPs) or the CABLE_PLUG (for SOP', SOP'' and _debugs) bits within the TX Parameters Register C

(TX_PARAM_C), depending on the SOP type that was received. Bit 5 in the packet header is taken from either the

PORT_DATA_ROLE bit (for SOPs) or set to zero (for SOP', SOP'' and _debugs), depending on the SOP type that was

received.

In order to avoid missing an auto response GoodCRC request, a flag is used. The flag is set with a request pulse from

the receiver and is cleared when the response is sent or aborted. Along with the request flag being set, the SOP type

and message ID of the request as well as the Soft Reset response indication are saved. In the event that there was a

Note:

Setting the PREAMBLE_LEN field to an odd value will cause violation of the USB PD Specification which

states “The preamble shall start with a “0” and shall end with a “1”.” An odd value will cause preamble to

start with a value of “0” but it will also end in a value of “0.” Setting this field to an odd value may or may

not lead to functional issues. Therefore, this field should be set to an even value to remain USB PD Spec-

ification compliant.

Note:

The CRC32 algorithm is described in the USB PD Specification.

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