UPD360 datasheet(113/221 Pages) MICROCHIP

113 / 221 page

 2016-2017 Microchip Technology Inc.

DS00002084C-page 113

UPD360

Note that the tx_queue_data[4:0] is passed as-is when tx_queue_data[5] is set to 1. Thus, software can send reserved

symbols for error testing. The only caveat is that hardware cannot be used to generate and insert CRC. In this case,

software should compute the necessary CRC32 and add it the data packet and skip the 0xFF code in the queue for CRC

insertion.

11.1.1.2.3

TX Queue Programming Sequence - AMDP

The following sequence should be used when programming a sequence in AMDP. This example assumes hardware

performs packet framing and CRC insertion.

Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous

TX request.

If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the

TX Control Register B (TX_CTL_B).

Write the two header bytes.

Write the payload data, if any.

Write the number of bytes to the TX Packet Length Register (TX_PKT_LEN).

Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)).

If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission.

Else: repeat step 6. Note: If an RX is in progress, the current TX may need to be abandoned.

TABLE 11-1:

RAW MODE DATA ENCODING

tx_queue_data[5:0]

Encoded Symbol

tx_queue_data[5:0]

Encoded Symbol

6’h00

5’b11110

6’h08

5’b10010

6’h01

5’b01001

6’h09

5’b10011

6’h02

5’b10100

6’h0A

5’b10110

6’h03

5’b10101

6’h0B

5’b10111

6’h04

5’b01010

6’h0C

5’b11010

6’h05

5’b01011

6’h0D

5’b11011

6’h06

5’b01110

6’h0E

5’b11100

6’h07

5’b01111

6’h0F

5’b11101

tx_queue_data[5:0]

K-Code

Transmitted Data

6’b1_11000

Sync-1

5’b11000

6’b1_10001

Sync-2

5’b10001

6’b1_01101

EOP

5’b01101

6’b1_00111

RST1

5’b00111

6’b1_11001

RST2

5’b11001

tx_queue_data[5:0]

Special Meaning

8’hFE

TX_STOP

8’hFF

TX_INS_CRC

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