UPD360 datasheet(114/221 Pages) MICROCHIP

114 / 221 page

UPD360

DS00002084C-page 114

 2016-2017 Microchip Technology Inc.

11.1.1.2.4

TX Queue Programming Sequence - RMDP

The following sequence should be used when programming a sequence in RMDP. This example assumes hardware

performs CRC insertion.

Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous

TX request.

If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the

TX Control Register B (TX_CTL_B).

Write the SOP K-Codes to the FIFO *Sync-1, Sync-1, Sync-1, Sync-2).

Write two header bytes, splitting each byte into nibbles.

Write the payload data, if any, splitting each byte into nibbles.

Write the value “0xFF” to insert the CRC.

Write the EOP K-Code (EOP).

Write the value “0xFE” to terminate the transmission. Failure to write this value will cause transmission to con-

tinue indefinitely looping on the TX buffer.

Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)).

10. If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission.

Else: repeat step 9. Note: If an RX is in progress, the current TX may need to be abandoned.

11.1.2

TX CONTROL

The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and

based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control

information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in

automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also

handles the selection of the SOP type that is to be transmitted.

11.1.2.1

Transmit Requests

There are four sources of transmit requests:

• GoodCRC Ack from the receiver for a soft-reset

• GoodCRC Ack from the receiver for a normal packet

• BIST error count message from the BIST receiver

• Transmit go from the software

11.1.2.2

Transmit Aborts

Once packet transmission is initiated, the device will power up the analog and then wait for the bus turn-around timers

and power-up timers to expire. During this wait, the transmission can be aborted by software and will be aborted by the

device, when a good packet (including soft-reset), a hard reset, or a cable reset (if enabled and the SOP type of the

pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received.

Once the bus turn-around time has expired (or if it was already expired) and the power up time is expired, the bus is

checked for idle. If the bus is idle, the transmission is started. If the bus is not idle, the transmission is discarded and,

typically, an abort status set. This discard can be disabled with the WAIT4LINE_IDLE bit in the TX Control Register A

(TX_CTL_A) for all packets and is also disabled for auto response triggered GoodCRC Acks for received soft-resets

(unless the feature is disabled via the DIS_SPCL_SR_GCRC_ACK bit).

If the transmission is not discarded due to the bus being non-idle, the device waits for the bus to become idle and then,

once again, waits the turn-around time. During the wait for bus idle, the transmission can be aborted by software and

will be aborted by the hardware if a good packet, a hard reset or a cable reset (if enabled and the SOP type of the pend-

ing TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received.

Software issued hard and cable resets are not aborted due to received good packets, hard resets or cable resets.

Note:

The value of the TX Packet Length Register (TX_PKT_LEN) is ignored for this mode since hardware knows

when to terminate the packet based on detection of TX_STOP control code.

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