UPD360 datasheet(111/221 Pages) MICROCHIP

111 / 221 page

 2016-2017 Microchip Technology Inc.

DS00002084C-page 111

UPD360

11.0

POWER DELIVERY MAC

The PD MAC implements certain features of the protocol layer and physical layer of the Universal Serial Bus Power

Delivery Specification. On one end the PD MAC interfaces to the software implementing the bulk of protocol and higher

level layers and on the other end it interfaces to a BMC encoder / decoder module.

In addition to the normal TX and RX functions, the PD MAC implements the test mode logic defined in the USB PD

specification (BIST).

The PD MAC supports the following features:

• Automatic TX Mode for packet framing and CRC32 insertion.

• Raw TX Mode for bit level packet control.

• Automatic GoodCRC response to received messages.

• Automatic BIST Error Count Message in BIST RX Mode.

• GoodCRCTimer implementation.

• Automatic retries with programmable retry count.

• Redundant receive packets automatically dropped in auto response mode.

• 74 byte TX queue.

• 128 byte RX queue.

• Programmable TX Bit-time. Allows for changing operating frequency.

• Programmable preamble length.

• BIST TX and RX logic.

• Programmable TX and RX queue modes - buffer mode and FIFO mode.

• CRC32 generator for TX.

• CRC32 calculator and comparator for RX.

11.1

PD MAC Transmitter

The PD MAC transmitter is comprised of three major blocks:

• TX Queue

• TX Control

• TX Comm

The TX Queue is where software loads the message to be transmitted.

The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and

based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control

information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in

automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also

handles the selection of the SOP type that is to be transmitted.

The TX Comm is comprised of a TX CRC generator, a 4b5b encoder, serializer, preamble generator, and TX bit timer.

It takes the nibble data, computes and inserts the CRC, 5b encodes, and generates the baseband serial data. Preamble

insertion is also performed by this logic.

The following sub-sections describe the various blocks and sub-blocks in more detail. Some of the supported TX fea-

tures are also described.

11.1.1

TX QUEUE

The TX Queue is where software loads the message to be transmitted. The following sub-sections describe the TX

Queue in more detail.

11.1.1.1

TX Queue Modes of Operation

The TX Queue's write interface (MCU side) has two modes of operation: FIFO Mode and Buffer Mode.

11.1.1.1.1

FIFO Mode

This mode is enabled by setting the EN_FMQ bit in the TX Control Register A (TX_CTL_A). In this mode, software writes

data into the TX Queue like a FIFO. Software can use any offset address in the range of 1800h-1849h (although 1800h

would be logical to use). The FIFO is 74 entries deep. Data written to the FIFO cannot be read back by software.

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